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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PCI1221 датащи(PDF) 53 Page - Texas Instruments |
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PCI1221 датащи(HTML) 53 Page - Texas Instruments |
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53 / 123 page  PCI1221 GHK/PDV PC CARD CONTROLLERS SCPS042 – JULY 1998 53 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CardBus latency timer register Bit 7 6 5 4 3 2 1 0 Name CardBus latency timer Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: CardBus latency timer Type: Read/write Offset: 1Bh (functions 0, 1) Default: 00h Description: This read/write register is programmed by the host system to specify the latency timer for the PCI1221 CardBus interface in units of CCLK cycles. When the PCI1221 is a CardBus initiator and asserts CFRAME, the CardBus latency timer begins counting. If the latency timer expires before the PCI1221 transaction has terminated, then the PCI1221 terminates the transaction at the end of the next data phase. A recommended minimum value for this register is 20h, which allows most transactions to be completed. memory base registers 0, 1 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Memory base registers 0, 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Memory base registers 0, 1 Type R/W R/W R/W R/W R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Memory base registers 0, 1 Type: Read only, read/write Offset: 1Ch, 24h Default: 0000 0000h Description: The Memory base registers indicate the lower address of a PCI memory address range. These registers are used by the PCI1221 to determine when to forward a memory transaction to the CardBus bus and when to forward a CardBus cycle to PCI. Bits 31-12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit PCI memory space on 4K-byte boundaries. Bits 11-0 are read only and always return 0s. Write transactions to these bits have no effect. Bits 8 and 9 of the bridge control register specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero for the PCI1221 to claim any memory transactions through CardBus memory windows (i.e., these windows are not enabled by default to pass the first 4K-bytes of memory to CardBus). |
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