PCI1221 datasheet(88/123 Pages) TI

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ExCA card status-change register (index 04h)

Bit

Name

ExCA card status change

Type

Default

ExCA card status change

Type:

Read only (see individual bit descriptions)

Offset:

CardBus socket address + 804h; Card A ExCA offset 04h

Card B ExCA offset 44h

Default:

00h

Description: The card status-change register controls interrupt routing for I/O interrupts as well as other

critical 16-bit PC Card functions. The register enables these interrupt sources to generate an

interrupt to the host. When the interrupt source is disabled, the corresponding bit in this

host, the interrupt service routine must read this register to determine the source of the

interrupt. The interrupt service routine is responsible for resetting the bits in this register as

well. Resetting a bit is accomplished by one of two methods: a read of this register or an

explicit write back of 1 to the status bit. The choice of these two methods is based on the

interrupt flag clear mode select, bit 2, in the global control register. See Table 43 for a

complete description of the register contents.

Table 43. ExCA Card Status-Change Register (Index 04h)

BIT

SIGNAL

TYPE

FUNCTION

7-4

RSVD

Reserved. Bits 7-4 are read only and return 0s when read. Write transactions have no effect.

CDCHANGE

Card detect change. Bit 3 indicates whether a change on CD1 or CD2 occurred at the PC Card

interface. This bit is encoded as:

0 = No change detected on either CD1 or CD2

1 = Change detected on either CD1 or CD2

READYCHANGE

Ready change. When a 16-bit memory is installed in the socket, bit 2 includes whether the source

of a PCI1221 interrupt was due to a change on READY at the PC Card interface, indicating that the

PC Card is now ready to accept new data. This bit is encoded as:

0 = No low-to-high transition detected on READY (default)

1 = Detected low-to-high transition on READY

When a 16-bit I/O card is installed, bit 2 is always 0.

BATWARN

Battery warning change. When a 16-bit memory card is installed in the socket, bit 1 indicates whether

the source of a PCI1221 interrupt was due to a battery-low warning condition. This bit is encoded as:

0 = No battery warning condition (default)

1 = Detected battery warning condition

When a 16-bit I/O card is installed, bit 1 is always 0.

BATDEAD

Battery dead or status change. When a 16-bit memory card is installed in the socket, bit 0 indicates

whether the source of a PCI1221 interrupt was due to a battery dead condition. This bit is encoded

as:

0 = STSCHG deasserted (default)

1 = STSCHG asserted

Ring indicate. When the PCI1221 is configured for ring indicate operation, bit 0 indicates the status

of RI.

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