HC705MC4GRSSLASHD datasheet(101/180 Pages) NXP

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Pulse Width Modulator

PWM Control Registers

General Release Specification

Pulse Width Modulator

Figure 10-6. PWM Waveforms (POLx = 0)

Mask (MSKx

[3:1])

When MEx is set, the MSKx bits establish mask values for pins that

are not selected by CSx. A mask value of 1 drives unselected PWM

subsystem pins high. A mask value of 0 drives unselected PWM

subsystem pins low. When MEx is clear, the mask bits have no effect.

If the mask feature is enabled (MEx =1), the mask bits also provide an

alternative method of generating 0% or 100% values. The

conventional method generates 100% duty cycle by inverting the

output polarity and simultaneously clearing the PWM data bits.

See Figure 10-7, Table 10-1, and Figure 10-8 for schematic, truth

table, and example waveform view for the PWM subsystem

multiplexer.

Channel Select (CSx

[3:1])

These bits select which pin or pins will receive the PWM waveform

output. Channel select has higher priority than mask enable. When

CSx[y] is set, the pin is selected and the PWMx output waveform will

be sent to the port logic. When CSx[y] is clear, the output will depend

on the MEx bit and the corresponding port register bit. See Figure

10-7, Table 10-1, and Figure 10-8 for schematic, truth table, and

example waveform view for the PWM subsystem multiplexer.

PWM DATA REGISTER = $00

PWM DATA REGISTER VALUE

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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