ADP1055ACPZ-R7 datasheet(115/140 Pages) AD

115 / 140 page

Data Sheet

ADP1055

Rev. A | Page 115 of 140

Table 195. Register 0xFE52—SR_DELAY

Bits

Bit Name

R/W

Description

[7:6]

SR blanking

R/W

These bits add blanking to the reverse current comparator from the falling edges of the SR LLM

edges. Adding dead time to the SR edges effectively gives additional blanking. When the SR

outputs are disabled upon a negative going zero crossing transition, they remain disabled for a

period of 327 μs to 754 μs to ensure that the comparator is not falsely triggered.

Bit 7

Bit 6

Blanking (ns)

120

160

[5:0]

SR driver delay

R/W

These bits specify the 6-bit representation of the SR delay in steps of 5 ns.

000000 = 0 ns.

000001 = 5 ns.

000010 = 10 ns.

…

111111 = 63 × 5 ns = 315 ns.

Table 196. Register 0xFE53—MODULATION_LIMIT

Bits

Bit Name

R/W

Description

Full bridge mode

R/W

Enable this bit when operating in full bridge mode. It affects the modulation high limit.

[6:0]

Modulation limits

R/W

This value sets the minimum/maximum modulation limits relative to the nominal edge value. The

resolution depends on the switching frequency range.

Switching Frequency Range (kHz)

Resolution Corresponding to LSB

48.8 to 97.7

97.7 to 195.3

195.3 to 390.6

390.6 to 781

fSW > 781

Table 197. Register 0xFE55—SYNC (Requires Use of the GO Bit in Register 0xFE00)

Bits

Bit Name

R/W

Description

Reserved

Reserved.

PLL disable

R/W

0 = enable SYNC function.

1 = disable SYNC function.

[5:2]

Reserved

Reserved.

Jitter enable

R/W

1 = enable jitter on clock (to randomize frequency components).

5 ns resolution

enable

R/W

0 = tSW varies in multiples of 10 ns (50% point is synchronized with 5 ns; see the External Frequency

Synchronization section).

1 = tSW varies in multiples of 5 ns.

Table 198. Register 0xFE56—DUTY_BAL_EDGESEL

Bits

Bit Name

R/W

Description

[7:4]

Positive integration

of PWM outputs

R/W

1 = selects the PWM outputs to be AND’ed together for positive integration

Bit 7 = OUTA

Bit 6 = OUTB

Bit 5 = OUTC

Bit 4 = OUTD

[3:0]

Negative integration

of PWM outputs

R/W

1 = selects the PWM outputs to be AND’ed together for negative integration

Bit 3 = OUTA

Bit 2 = OUTB

Bit 1 = OUTC

Bit 0 = OUTD

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