ADP1055ACPZ-R7 datasheet(46/140 Pages) AD

46 / 140 page

ADP1055

Data Sheet

Rev. A | Page 46 of 140

POWER SUPPLY CALIBRATION AND TRIM

The ADP1055 allows the entire power supply to be calibrated

and trimmed digitally in the production environment. The device

can calibrate items including the output voltage, input voltage,

input current, and input power, and it can trim for tolerance

errors introduced by sense resistors, current transformers, and

resistor dividers, as well as for its own internal circuitry.

The ADP1055 is factory trimmed, but it can be retrimmed by

the user to compensate for the errors introduced by external

components. The ADP1055 GUI allows the user to revert the

trim settings to their factory default values using the RESTORE_

DEFAULT_ALL command (Register 0x12). To unlock the trim

registers for write access, perform consecutive writes to TRIM_

PASSWORD (Register 0xD6) using the correct password. This

password is the same one used to unlock the EEPROM using

EEPROM_PASSWORD (Register 0xD5). The factory default

password is 0xFF.

The ADP1055 allows the user enough trim capability to trim for

external components with a tolerance of 0.5% or better. If the

ADP1055 is not trimmed in the production environment, it is

recommended that components with a tolerance of 0.1% or

better be used for the inputs to CS1, VFF, and VS± to meet the

data sheet specifications.

VOLTAGE CALIBRATION AND TRIM

The voltage sense point can be calibrated digitally to minimize

errors due to external components using the VOUT_TRIM

command (Register 0x22). This calibration can be performed in

the production environment, and the settings can be stored in

the EEPROM of the ADP1055.

The voltage sense inputs are optimized for sensing signals at

1 V. In a 12 V system, a 12:1 resistor divider is required to reduce

the 12 V signal down to 1 V. It is recommended that the output

voltage of the power supply be reduced to 1 V at this pin for best

performance. The tolerance of the resistor divider introduces

errors that must be trimmed. The ADP1055 has enough trim

range to trim out errors introduced by resistors with a tolerance

of 0.5% or better.

The VS ADC produces a digital code equal to VS±/1.6 × 4096.

The VS± inputs require a gain trim. The following steps should

be performed before any other trim routine.

Set the output regulation point to 100% of the nominal

value.

Enable the power supply with no load current. The power

supply output voltage is divided down by the resistor divider

to give 1 V across the VS+ and VS− differential input pins.

Adjust the VS trim register (Register 0xFE80) until the VS±

voltage value in Register 0xFE97[13:2] reads 1010 0000 0000

when there is 1.0 V on the pins.

CS1 TRIM

The current sense can be calibrated using a dc or ac signal to

minimize errors due to external components.

Using a DC Signal

A known voltage (Vx) is applied at the CS1 pin. The CS1 ADC

should output a digital code equal to Vx/1.6 × 4096. Adjust the

CS1 gain trim register (Register 0xFE82) until the CS1 ADC

value in Register 0xFE98 reads the correct digital code. For

example, Register 0xFE98[13:2] reads a value of 1010 0000 0000

when there is 1.0 V on the CS1 pin.

Using an AC Signal

A known current (Ix) is applied to the CS1 pin. This current

passes through a current transformer, a diode rectifier, and an

external resistor (RCS1) to convert the current information to a

voltage (Vx). This voltage is fed into the CS1 pin. The voltage

(Vx) is calculated as follows:

Vx = Ix × (N1/N2) × RCS1

where N1/N2 is the turns ratio of the current transformer.

The CS1 ADC outputs a digital code equal to Vx/1.6 × 4096.

Adjust the CS1 gain trim register (Register 0xFE82) until the

CS1 ADC value in Register 0xFE98 reads the correct digital code.

VFF CALIBRATION AND TRIM

The VFF feedforward ADC (see Figure 32) is used for voltage

line feedforward and is factory trimmed. This ADC cannot be

trimmed by the user.

The VFF slow ADC requires a gain trim.

Enable the power supply with full load current at the nominal

input voltage. The secondary peak reverse voltage on the

output rectifiers is filtered by an external RCD circuit (see

Figure 32).

To trim the VFF ADC, reverse-calculate the primary

voltage as follows:

VPRIMARY = Vx × (R1 + R2)/R2 × (N1/N2)

where:

Vx is the voltage at the VFF pin.

N1/N2 is the turns ratio. }

Adjust the VFF gain trim register (Register 0xFE81) until

this calculated voltage is equal to the desired primary input

voltage. For example, Register 0xFE96[13:2] reads a value

of 1010 0000 0000 when there is 1.0 V on the VFF pin.

The resistors in Figure 32 are sized such that the first time

constant, RC, is long enough to prevent overcharging of the

capacitor (roughly 200 ns in a typical application), whereas the

second time constant, (R1 + R2) × C, is long enough to keep the

average voltage constant during the rectifier off time.

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