ADP1055ACPZ-R7 datasheet(16/140 Pages) AD

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ADP1055

Data Sheet

Rev. A | Page 16 of 140

CONTROLLER ARCHITECTURE

The ADP1055 is an application specific digital controller based

on finite state machine (FSM) architecture. The ADP1055 supports

a subset of the PMBus Revision 1.2 standard and also has extended

manufacturer specific commands to provide a feature rich digital

power product.

Dedicated ADCs and comparators constitute the analog front

end of the controller, feeding information to the digital core. The

information is processed and used to generate the programmable

PWM signals and to take action for various features such as light

load or overvoltage/overcurrent protection.

The ADP1055 has six PWM outputs: OUTA to OUTD for the

primary side switches and SR1 and SR2 for the secondary side

synchronous rectifiers. The ADP1055 allows individual

programming of the PWM outputs to form the timing of the

power switches for any power topology, such as full bridge, full

bridge phase shifted, current doubler, or active clamp.

Primary side information (current or voltage) is sensed and

processed via the CS1 and VFF pins, whereas secondary side

information is obtained via the CS2±, ISHARE, VS±, and OVP

pins. A dedicated temperature sensor uses the JTD and JRTN

pins. The input voltage is measured using the VFF pin and is

used for line voltage feedforward. Extensive fault protection

schemes are provided, and the controller also has a black box to

record the state of the device (all sensor information including

voltages, currents, temperatures, and flags) upon shutdown.

I2C/PMBus communication is facilitated by the SDA, SCL, and

SMBALRT pins. Four GPIO pins can be used as flag output

signals or as an interrupt service routine (ISR) to trigger a

PMBus fault action. The CTRL pin is used as described in the

PMBus specification.

Detailed descriptions of all ADP1055 features are provided in

the Theory of Operation section.

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