ADP1055ACPZ-R7 datasheet(91/140 Pages) AD

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Data Sheet

ADP1055

Rev. A | Page 91 of 140

Bits

Bit Name

R/W

Description

[1:0]

Volt-second balance

gain setting

R/W

These bits set the gain of the volt-second balance circuit. The gain can be changed by a factor

of 64. When these bits are set to 00, it takes approximately 700 ms to achieve volt-second balance.

When these bits are set to 11, it takes approximately 10 ms to achieve volt-second balance.

Bit 1

Bit 0

Volt-Second Balance Gain

Table 151. Register 0xFE26—VSBAL_OUTA_B

Bits

Bit Name

R/W

Description

Modulate enable, t1

R/W

Setting this bit enables modulation from balance control on the OUTA rising edge, t1.

t1 sign

R/W

0 = positive sign. Increase of balance control modulation moves t1 right.

1 = negative sign. Increase of balance control modulation moves t1 left.

Modulate enable, t2

R/W

Setting this bit enables modulation from balance control on the OUTA falling edge, t2.

t2 sign

R/W

0 = positive sign. Increase of balance control modulation moves t2 right.

1 = negative sign. Increase of balance control modulation moves t2 left.

Modulate enable, t3

R/W

Setting this bit enables modulation from balance control on the OUTB rising edge, t3.

t3 sign

R/W

0 = positive sign. Increase of balance control modulation moves t3 right.

1 = negative sign. Increase of balance control modulation moves t3 left.

Modulate enable, t4

R/W

Setting this bit enables modulation from balance control on the OUTB falling edge, t4.

t4 sign

R/W

0 = positive sign. Increase of balance control modulation moves t4 right.

1 = negative sign. Increase of balance control modulation moves t4 left.

Table 152. Register 0xFE27—VSBAL_OUTC_D

Bits

Bit Name

R/W

Description

Modulate enable, t5

R/W

Setting this bit enables modulation from balance control on the OUTC rising edge, t5.

t5 sign

R/W

0 = positive sign. Increase of balance control modulation moves t5 right.

1 = negative sign. Increase of balance control modulation moves t5 left.

Modulate enable, t6

R/W

Setting this bit enables modulation from balance control on the OUTC falling edge, t6.

t6 sign

R/W

0 = positive sign. Increase of balance control modulation moves t6 right.

1 = negative sign. Increase of balance control modulation moves t6 left.

Modulate enable, t7

R/W

Setting this bit enables modulation from balance control on the OUTD rising edge, t7.

t7 sign

R/W

0 = positive sign. Increase of balance control modulation moves t7 right.

1 = negative sign. Increase of balance control modulation moves t7 left.

Modulate enable, t8

R/W

Setting this bit enables modulation from balance control on the OUTD falling edge, t8.

t8 sign

R/W

0 = positive sign. Increase of balance control modulation moves t8 right.

1 = negative sign. Increase of balance control modulation moves t8 left.

Table 153. Register 0xFE28—VSBAL_SR1_2

Bits

Bit Name

R/W

Description

Modulate enable, t9

R/W

Setting this bit enables modulation from balance control on the SR1 rising edge, t9.

t9 sign

R/W

0 = positive sign. Increase of balance control modulation moves t9 right.

1 = negative sign. Increase of balance control modulation moves t9 left.

Modulate enable, t10

R/W

Setting this bit enables modulation from balance control on the SR1 falling edge, t10.

t10 sign

R/W

0 = positive sign. Increase of balance control modulation moves t10 right.

1 = negative sign. Increase of balance control modulation moves t10 left.

Modulate enable, t11

R/W

Setting this bit enables modulation from balance control on the SR2 rising edge, t11.

t11 sign

R/W

0 = positive sign. Increase of balance control modulation moves t11 right.

1 = negative sign. Increase of balance control modulation moves t11 left.

Modulate enable, t12

R/W

Setting this bit enables modulation from balance control on the SR2 falling edge, t12.

t12 sign

R/W

0 = positive sign. Increase of balance control modulation moves t12 right.

1 = negative sign. Increase of balance control modulation moves t12 left.

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