ADP1055ACPZ-R7 datasheet(27/140 Pages) AD

27 / 140 page

Data Sheet

ADP1055

Rev. A | Page 27 of 140

Thresholds and limits can be set for CS2 using these PMBus

commands: IOUT_OC_FAULT_LIMIT (Register 0x46) and

IOUT_OC_WARN_LIMIT (Register 0x4A). The fault response

is programmable in Register 0x47.

SECONDARY FAST OVERCURRENT PROTECTION

The input signal on the CS2± pins is also fed into two comparators

for fast OCP protection. The fast OCP comparator is used to

limit the instantaneous secondary current in either the positive

or the negative direction. The CS2 OCP comparator also features a

programmable timeout condition (set in Register 0xFE4F[6:4]),

which specifies that the CS2 fast OCP condition must be present in

consecutive switching cycles before the IOUT_OC_FAST_FAULT

flag is set.

When the CS2 fast OCP comparator is used to sense the output

inductor current instead of the load current (see Figure 1), the

comparator can be used for cycle-by-cycle peak current limiting

of the inductor current. Cycle-by-cycle peak current limiting is

executed by the termination of the PWM outputs (OUTA to

OUTD) to disable power transfer to the secondary side. In an

isolated buck derived topology, the inductor current during the

on time of the primary switch is a fraction of the inductor current;

this feature can be used when the CS1 pin is not used. The CS2

fast OCP threshold can be set in steps of 9.52 mV for the 480 mV

CS2 ADC range and in steps of 0.952 mV for the 30 mV and

60 mV CS2 ADC ranges using Register 0xFE2D.

SECONDARY FAST REVERSE CURRENT PROTECTION

A programmable comparator is used to detect reverse current.

The comparator can also be used for diode emulation mode to

improve light load efficiency. The IOUT_UC_FAST fault is set

when the CS2 reverse comparator is asserted. After it is set, the

IOUT_UC_FAST fault is cleared between 328 μs and 656 μs

after the deassertion of the CS2 reverse comparator.

For all three CS2 ADC ranges (30 mV, 60 mV, and 480 mV), the

threshold is programmed in Register 0xFE2E[7:2], and the

debounce is programmed in Register 0xFE2E[1:0].

The operation of diode emulation mode depends on the accurate

sensing of the zero crossing of the inductor current, which in

turn is dependent on proper sensing of the inductor current

through the sense resistor. The accuracy of the fast reverse current

protection is heavily dependent on the sensing of the inductor

current; proper layout techniques (Kelvin sensing) must be

followed.

The fast reverse current comparator range is extended to a

positive range (0 mV to 30 mV) in addition to the negative

range (−30 mV to 0 mV). With this dual range, an accurate

sensing of the zero crossing can be tweaked and trimmed to

turn off the synchronous rectifiers at exactly the zero crossing

of the inductor current by compensating for the gate driver

delay and layout inadequacies and by ensuring that there is no

excessive voltage stress or voltage spike across the devices.

FEEDFORWARD AND INPUT VOLTAGE SENSE

The ADP1055 supports voltage line feedforward control to

improve line transient performance.

The feedforward scheme modifies the modulation value based

on the VFF voltage. When the VFF input is 1 V, the line feed-

forward has no effect. For example, if the digital filter output

remains unchanged and the VFF voltage changes to 50% of its

original value (but still higher than 0.5 V), the modulation of the

falling edges of OUTA to OUTD doubles (see Figure 35). The

voltage line feedforward function is optional and is program-

mable using Register 0xFE29 and Register 0xFECD[2:0]. It is

recommended that feedforward be enabled during soft start.

The VFF voltage must be set to 1 V when the nominal input

voltage is applied. The voltage at the VFF pin is sampled synchro-

nously with the switching period and, therefore, the decision to

modify the PWM outputs based on input voltage is performed at

this rate. Typically, the feedforward block can detect and respond

to a 3% change in input voltage and make a change to the PWM

outputs approximately every 1 μs.

To prevent false triggering of the feedforward block due to

noise/voltage spikes on the VFF pin that are carried from the

switch node, a small filter capacitor may be needed. The filter

capacitor should not be too large, and the time constant should

typically be much less than 1 μs. An additional ADC connected

to the VFF pin is used to report the ADC value and therefore,

the input value, using the resistive dividers. The primary input

voltage can be calculated by multiplying Vx by the turns ratio

(N1/N2), as follows:

VPRIMARY = Vx × (R1 + R2)/R2 × (N1/N2)

For fault comparison, the input voltage is monitored using the

VFF ADC, and the 9 MSBs (VFF_VALUE, Register 0xFE96[13:2])

are converted into PMBus format and compared to the threshold

to make a fault decision. Fault limits and their responses can be

set using PMBus commands such as VIN_UV_FAULT_LIMIT

(Register 0x59), VIN_OV_FAULT_LIMIT (Register 0x55),

VIN_UV_FAULT_RESPONSE (Register 0x5A), and

VIN_OV_FAULT_RESPONSE (Register 0x56).

Figure 35. Feedforward Control on Modulation

VFF

DIGITAL

FILTER

OUTPUT

OUTx

tMODULATION

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