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ADP1055ACPZ-R7 датащи(PDF) 88 Page - Analog Devices

номер детали ADP1055ACPZ-R7
подробное описание детали  Digital Controller for Power Supply Applications with PMBus Interface
PDF  140 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
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ADP1055ACPZ-R7 датащи(HTML) 88 Page - Analog Devices

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ADP1055
Data Sheet
Rev. A | Page 88 of 140
Table 142. Register 0xFE15, Register 0xFE17—SR1_REDGE_SETTING, SR2_REDGE_SETTING (Requires Use of the GO Bit in
Register 0xFE00)
Bits
Bit Name
R/W
Description
[15:4]
t9, t11
R/W
This register contains the 12-bit t9, t11 time. Each LSB corresponds to 5 ns resolution.
The minimum and maximum possible duty cycle is 0% and 100%, respectively.
3
Modulate enable
R/W
1 = PWM modulation acts on the t9, t11 edge.
0 = no PWM modulation of the t9, t11 edge.
2
t9, t11 sign
R/W
1 = negative sign. Increase of PWM modulation moves t9, t11 right.
0 = positive sign. Increase of PWM modulation moves t9, t11 left.
[1:0]
Reserved
R
Reserved.
Table 143. Register 0xFE16, Register 0xFE18—SR1_FEDGE_SETTING, SR2_FEDGE_SETTING (Requires Use of the GO Bit in
Register 0xFE00)
Bits
Bit Name
R/W
Description
[15:4]
t10, t12
R/W
This register contains the 12-bit t10, t12 time. Each LSB corresponds to 5 ns resolution.
3
Modulate enable
R/W
1 = PWM modulation acts on the t10, t12 edge.
0 = no PWM modulation of the t10, t12 edge.
2
t10, t12 sign
R/W
1 = negative sign. Increase of PWM modulation moves t10, t12 right.
0 = positive sign. Increase of PWM modulation moves t10, t12 left.
[1:0]
Reserved
R
Reserved.
Table 144. Register 0xFE19, Register 0xFE1B—SR1_REDGE_LLM_SETTING, SR2_REDGE_LLM_SETTING (Requires Use of the
GO Bit in Register 0xFE00)
Bits
Bit Name
R/W
Description
[15:4]
t9, t11
R/W
This register contains the 12-bit t9, t11 time. Each LSB corresponds to 5 ns resolution. This is the
SR setting in light load mode.
The minimum and maximum possible duty cycle is 0% and 100%, respectively.
3
Modulate enable
R/W
1 = PWM modulation acts on the t9, t11 edge.
0 = no PWM modulation of the t9, t11 edge.
2
t9, t11 sign
R/W
1 = negative sign. Increase of PWM modulation moves t9, t11 right.
0 = positive sign. Increase of PWM modulation moves t9, t11 left.
[1:0]
Reserved
R
Reserved.
Table 145. Register 0xFE1A, Register 0xFE1C—SR1_FEDGE_LLM_SETTING, SR2_FEDGE_LLM_SETTING (Requires Use of the
GO Bit in Register 0xFE00)
Bits
Bit Name
R/W
Description
[15:4]
t10, t12
R/W
This register contains the 12-bit t10, t12 time. Each LSB corresponds to 5 ns resolution. This is the
SR setting in light load mode.
The minimum and maximum possible duty cycle is 0% and 100%, respectively.
3
Modulate Enable
R/W
1 = PWM modulation acts on the t10, t12 edge.
0 = no PWM modulation of the t10, t12 edge.
2
t10, t12 sign
R/W
1 = negative sign. Increase of PWM modulation moves t10, t12 right.
0 = positive sign. Increase of PWM modulation moves t10, t12 left.
[1:0]
Reserved
R
Reserved.



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