ADP1055ACPZ-R7 datasheet(111/140 Pages) AD

111 / 140 page

Data Sheet

ADP1055

Rev. A | Page 111 of 140

Table 186. Register 0xFE49—PWM_DISABLE_SETTING

Bits

Bit Name

R/W

Description

[7:6]

Reserved

Reserved.

SR2 disable

R/W

Setting this bit disables the SR2 output.

SR1 disable

R/W

Setting this bit disables the SR1 output.

OUTD disable

R/W

Setting this bit disables the OUTD output.

OUTC disable

R/W

Setting this bit disables the OUTC output.

OUTB disable

R/W

Setting this bit disables the OUTB output.

OUTA disable

R/W

Setting this bit disables the OUTA output.

Table 187. Register 0xFE4A—FILTER_TRANSITION (Requires Use of the GO Bit in Register 0xFE00)

Bits

Bit Name

R/W

Description

Overshoot

protection

R/W

0 = disable setpoint reference tracking.

1 = enable setpoint reference tracking (see the Integrator Windup and Output Voltage Regulation

Loss (Overshoot Protection) section).

Overshoot speed

R/W

0 = if VOUT is out of regulation for 96 out of 128 switching cycles, the reference moves to the last

known value of VOUT (9-bit precision) and tries to return to regulation at a controlled rate given by

the VOUT_TRANSITION_RATE command.

1 = if VOUT is out of regulation for 48 out of 64 switching cycles, VREF tracks VOUT (9-bit precision).

Double update rate affects this register.

[5:3]

HF ADC

configuration

R/W

000 = autocorrection loop disabled.

001 = autocorrection loop bandwidth set to approximately 9 Hz.

010 = autocorrection loop bandwidth set to approximately 19 Hz.

011 = autocorrection loop bandwidth set to approximately 37 Hz.

100 = autocorrection loop bandwidth set to approximately 75 Hz.

101 = autocorrection loop bandwidth set to approximately 150 Hz.

110 = autocorrection loop bandwidth set to approximately 300 Hz.

111 = autocorrection loop bandwidth set to approximately 600 Hz.

Enable soft transition

R/W

Enables soft transition between filter settings to minimize output transients. All four parameters of

each filter are linearly transitioned to the new value.

[1:0]

Transition speed

R/W

The filter changes in 32 steps, with one step applied at the interval specified by these bits.

Bit 1

Bit 0

Speed

32 × tSW (total transition time = 32 × 32 × tSW = 1024 × tSW)

8 × tSW (total transition time = 8 × 32 = 256 × tSW)

2 × tSW (total = 64 × tSW)

1 × tSW (total = 32 × tSW)

Table 188. Register 0xFE4B—DEEP_LLM_SETTING

Bits

Bit Name

R/W

Description

[7:5]

Deep LLM thresholds

R/W

These bits set the load current limit on the CS2 ADC below which SR1 and SR2 enter deep light

load mode. The averaging time, debounce, and hysteresis are programmed in Register 0xFE4B.

SR outputs are always off in pulse skip mode.

Bit 7

Bit 6

Bit 5

Thresholds (LSBs)

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