ADP1055ACPZ-R7 datasheet(93/140 Pages) AD

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Data Sheet

ADP1055

Rev. A | Page 93 of 140

Table 157. Register 0xFE2C—IIN_OC_FAST_SETTING

Bits

Bit Name

R/W

Description

[7:3]

Reserved

Reserved.

Threshold

R/W

0 = 1.2 V range.

1 = 250 mV range.

[1:0]

Debounce

R/W

Bit 1

Bit 0

Debounce Time

0 ns

40 ns

80 ns

120 ns

Table 158. Register 0xFE2D—IOUT_OC_FAST_SETTING

Bits

Bit Name

R/W

Description

[7:2]

Threshold

R/W

When the ADC range is 480 mV, LSB = 600/63 = 9.52 mV.

When the ADC range is 30 mV or 60 mV, LSB = 60/63 = 0.952 mV.

Threshold = LSB × Register 0xFE2D[7:2].

[1:0]

Debounce

R/W

Bit 1

Bit 0

Debounce Time

0 ns

40 ns

200 ns

400 ns

Table 159. Register 0xFE2E—IOUT_UC_FAST_SETTING

Bits

Bit Name

R/W

Description

[7:2]

Threshold

R/W

|LSB| = 30/63 = 0.476 mV.

Range is +30 mV to −30 mV in 64 steps.

Polarity = 0: Threshold = − 0.477 mV × Register 0xFE2E[7:2].

Polarity = 1: Threshold = + 0.472 mV × Register 0xFE2E [7:2].

Note that the IOUT_UC_FAST fault is set when the CS2 reverse comparator is asserted for the

minimum debounce programmed time. Once set, the IOUT_UC_FAST fault is cleared from

327 μs to 656 μs following the deassertion of the CS2 reverse comparator.

Polarity

R/W

1 = 0 to +30 mV range.

0 = 0 to −30 mV range.

Debounce

R/W

The debounce setting is set by Register 0xFE2D[1:0]. For example, if Register 0xFE2D[1:0] = 10,

the IOUT_OC_FAST_SETTING is 200 ns and the IOUT_UC_FAST_SETTING is 800 ns.

00 = 40 ns.

01 = 200 ns.

10 = 800 ns.

11 = 1200 ns.

Table 160. Register 0xFE2F—VOUT_OV_FAST_SETTING

Bits

Bit Name

R/W

Description

[7:2]

Threshold

R/W

64 steps: Threshold = 0.8 + (Register 0xFE2F[7:2]) × 0.8/63.

[1:0]

Debounce

R/W

These bits set the debounce time.

Bit 1

Bit 0

Typical Debounce Time

40 ns

2 μs + 1 μs

5 μs + 1 μs

10 μs + 1 μs

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