ADP1055ACPZ-R7 datasheet(31/140 Pages) AD

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Data Sheet

ADP1055

Rev. A | Page 31 of 140

GPIO3 AND GPIO4 AS SNUBBER PWM OUTPUTS

The GPIO3 and GPIO4 pins of the ADP1055 can be configured

as two signals used for an active snubber. This circuitry can be

used to provide a drive signals for an active clamp.

Snubber Configuration

The on time of the snubber and the dead time of the snubber

signals can be programmed using Register 0xFE63 and

turn on after a selectable dead time (0 ns to 315 ns in steps of

5 ns, programmable using Register 0xFE64[5:0]). Using

on one of the following:



Falling edge of SR1 or SR2 signal



Falling edge of OUTC and OUTD

The snubber signal stays on for a fixed value regardless of the

duty cycle and load condition programmed in Register 0xFE63.

However, the snubber signal is toggled as soon as it encounters

the next SRx rising edge or the next OUTx falling edge, even if

the programmed on time is of a greater value.

Figure 45. Active Clamp Snubber Configured on SRx Signals

Figure 46. Active Clamp Snubber Configured on OUTx Signals

Miscellaneous Snubber Configuration

Using Register 0xFE64[7:6]), the snubber configuration can be

set to one of these options:



Option 1: Both GPIO3 and GPIO4 are configured as regular

signals, as described in the GPIO and PGOOD Signals section

(see Figure 47).



Option 2: GPIO3 is configured as an active snubber

PWM output; GPIO4 is configured as a regular signal

(see Figure 48).



Option 3: GPIO3 is configured as a regular signal; GPIO4 is

configured as an active snubber PWM output (see Figure 49).



Option 4: Both GPIO3 and GPIO4 are configured as active

snubber PWM outputs (see Figure 50).

Figure 47. Option 1: GPIO3 and GPIO4 Configured as Regular Signals

Figure 48. Option 2: GPIO3 Configured as an Active Snubber PWM Output;

GPIO4 Configured as a Regular Signal

Figure 49. Option 3: GPIO3 Configured as a Regular Signal;

GPIO4 Configured as an Active Snubber PWM Output

Figure 50. Option 4: GPIO3 and GPIO4 Configured

as Active Snubber PWM Outputs

The GPIO polarity bit can be configured using the same bits

described in the GPIO and PGOOD Signals section. The

polarity bit allows true versatility with the use of either P channel

or N channel FETs, depending on the application. These PWM

signals can be blanked during soft start and soft stop using

active as long as the system does not shut down in response to a

fault condition or a PSOFF command is issued.

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