ADP1055ACPZ-R7 datasheet(112/140 Pages) AD

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ADP1055

Data Sheet

Rev. A | Page 112 of 140

Bits

Bit Name

R/W

Description

[4:3]

Deep light load mode

averaging speed

R/W

Sets the averaging speed and resolution used for the deep light load mode thresholds. Faster

speed corresponds to lower resolution, and therefore to smaller accuracy of the threshold.

Bit 4

Bit 3

Speed (μs)

37.5 (six bits)

82 (seven bits)

163 (eight bits)

327 (nine bits)

[2:1]

Deep light load mode

hysteresis

R/W

Sets the amount of hysteresis applied to the deep light load mode thresholds. The size of the

LSB is affected by the speed and resolution selected in Bits[4:3]. For example, if the ADC range

of 30 mV is used with 8-bit resolution, the LSB size is 30 mV/28 = 117.187 μV.

Bit 2

Bit 1

LSBs

Fast phase-in

R/W

0 = SR transition speed is always the value programmed during all transitions, as set by

1 = the SR transition speed is the value programmed in Register 0xFE5F[7:4] for the first

transition process (whenever that occurs after PSON according to the settings), but for every

subsequent transition, the SR outputs transition at the fastest speed, that is, 5 ns/tSW.

Table 189. Register 0xFE4C—DEEP_LLM_DISABLE_SETTING

Bits

Bit Name

R/W

Description

SR phase-in enable

R/W

0 = disable SR phase-in.

1 = enable SR phase-in.

OUTD disable

R/W

Setting this bit means that OUTD is disabled if the load current drops below the deep light load

threshold.

OUTC disable

R/W

Setting this bit means that OUTC is disabled if the load current drops below the deep light load

threshold.

OUTB disable

R/W

Setting this bit means that OUTB is disabled if the load current drops below the deep light load

threshold.

OUTA disable

R/W

Setting this bit means that OUTA is disabled if the load current drops below the deep light load

threshold.

SR2 disable

R/W

Setting this bit means that SR2 are disabled if the load current drops below the deep light load

threshold.

SRs enable during soft

stop

R/W

Setting this bit means that SR2 are disabled if the load current drops below the deep light load

threshold.

SRs enable during soft

stop

R/W

Setting this bit reenables the SRs during soft stop to facilitate discharging the load. The

recommended setting is 1.

Table 190. Register 0xFE4D—OVP_FAULT_CONFIG

Bits

Bit Name

R/W

Description

VDD/VCORE OV fault ignore

R/W

0 = VDD OV and VCORE OV flags are not ignored

1 = VDD OV and VCORE OV flags are ignored

VDD/VCORE OV restart

R/W

0 = do not download EEPROM again following a fault shutdown

1 = download EEPROM following a fault shutdown

VDD/VCORE OV debounce

R/W

0 = 2 μs + 1 μs debounce

1 = 500 μs + 10 μs debounce

VDD UV debounce

R/W

0 = no debounce

1 = 120 ns debounce

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