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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

207

Renesas Technology Corp.

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Overview of standard serial I/O mode 1 (clock synchronous)

In standard serial I/O mode 1, software commands, addresses and data are input and output between

the microcomputer and peripheral units (serial programer, etc.) using 4-wire clock-synchronized serial I/

O (UART1). Standard serial I/O mode 1 is entered by releasing the reset with the P65 (CLK1) pin “H” level

(and P86 (CE) pin and the CNVss pin are in “H” level).

When receiving software commands, addresses and program data are synchronized with the rising edge

of the transfer clock that is input to the CLK1 pin, and are then input to the RXD1 pin. When transmitting,

read data and status are synchronized with the falling edge of the transfer clock, and output from the

TxD1 pin. The data transfer is in 8-bit units with LSB first.

The TxD1 pin is a CMOS level output.

When the device is busy, such as during transmission, reception, erasing or program execution, the

RTS1 (BUSY) pin is “H” level. Accordingly, always start the next transfer after the RTS1 (BUSY) pin is “L”

level.

Also, data and status registers in memory can be read after inputting software commands. Status, such

as the operating state of the flash memory or whether a program or erase operation ended successfully

or not, can be checked by reading the status register. The following table shows the software com-

mands, status registers, etc. in serial I/O mode 1.

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