M16CSLASH26 datasheet(194/239 Pages) RENESAS

194 / 239 page

Renesas Technology Corp.

CPU Rewrite Mode (Flash Memory Version)

188

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

Erase-Suspend Feature

The M16C/26 Flash ROM has been designed to be more compact and require a smaller layout footprint.

This, as a result, causes longer erase times. The M16C/26 Flash ROM is however not available/acces-

sible during an erase operation. This may sometimes cause time critical interrupt driven operations re-

quiring data/program in the flash to not be satisfied during the erase operation.

To circumvent this issue, the M16C/26 Flash ROM offers a new 'erase-suspend' feature which allows the

erase operation to be suspended, and access made available to the flash. The erase operation may

subsequently be resumed via software.

There are CPU erase/write (CPUEW) modes available EW0 (execution out of RAM) and EW1 (execution

out of FLASH). The erase-suspend feature is different in each of these modes. Please note that 1-wait

needs to be set in CPUEW operations.

EW0:

In EW0, program code is executed out of the RAM. After the erase command has been executed,

program execution continues in the RAM. As stated earlier the FLASH is not accessible during an

erase operation. If there is a request for data/code from the FLASH (via a maskable peripheral/exter-

nal interrupt), the interrupt must first request an erase-suspend. This is achieved by setting bits

FMR40 (SUSPEND_ENABLE) and FMR41 (SUSPEND_REQUEST). The routine then polls FMR46

(SUSPENDL) until it is set. At this point the erase has been suspended and the flash is accessible.

Once the required accesses are complete FMR41 (SUSPEND_REQUEST) is cleared and the routine

is completed. The erase operation resumes and continues to completion or until another erase-sus-

pend request occurs.

User actions:

1.0 Execute erase command out of RAM.

2.0 Maskable Interrupt request.

2.1 Set FMR40 & FMR41.

2.2 Poll FMR46 until '1'.

2.3 Access flash data/code.

2.4 Clear FMR41.

2.5 Return

3.0 Continue execution out of RAM

FMR40 may also be set before the erase command is executed, instead of in the interrupt routine.

M16C/26 датащи(PDF) 194 Page - Renesas Technology Corp