M16CSLASH26 datasheet(190/239 Pages) RENESAS

190 / 239 page

Renesas Technology Corp.

Flash Memory

184

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

Table 1.19.1. Outline performance of the M16C/26 (flash memory version)

Outline Performance

Table 1.19.1 shows the outline performance of the M16C/26 (flash memory version).

Item

Flash memory operation mode

Erase block

division

Write method

Erase method

Erase/Write (E/W) control method

Protect method

Number of commands

Erase/Write count (Notes 1, 2)

ROM code protect

Performance

Three user modes (standard serial I/O, CPU rewrite, parallel I/O)

See Figure 1.19.1

In units of word.

Block erase

E/W control by software command

Two 8Kbyte user by register lock bit (FMR02)

5 commands

Depends on device code (see Table 1.2b)

Parallel I/O and standard serial I/O modes are supported.

Note 1: Block A and Block B are 10,000 times E/W. All other blocks are 1000 times E/W. (Under

development; mass production scheduled to start in the 3rd quarter of 2003.)

Note 2: Definition of E/W times:

The E/W times are defined to be per-block erasure times. For example, assume a case whereby a

4-Kbyte Block A is programmed one word at a time and erased once all 2048 write operations

have completed. In this case, the block is considered to have been written and erased once.

If a product is 100 times E/W, each block in it can be erased up to 100 times. When 10,000 times

E/W, Block A and Block B can each be erased up to 10,000 times. All other blocks can each be

erased up to 1000 times.

User ROM area

Data Retention

10 years

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