XIO2001IPNP datasheet(115/145 Pages) TI2

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power source for this clamp rail is a standard digital supply. The power source for this clamp rail is a standard

digital supply. The PCIR terminals should be connected to the digital supply via an inline 1 k Ω resistor. A 0.1- μ

F decoupling capacitor is also recommended at each PCIR terminal.

If PCIR is attached to a 5.0-V supply, the XIO2001 will only output 3.3-V amplitude signals on the PCI bus. The

received PCI bus signal amplitudes may be either 3.3 V or 5.0 V. The PCI bus I/O cells are 5.0-V tolerant and

the XIO2001 device is not damaged by 5.0-V input signal amplitudes.

9.2.1.1.2 Combined Power Outputs

To support VAUX system requirements, the XIO2001 internally combines main power with VAUX power. There are

three combined power rails in the XIO2001. These three power rails are distributed to the analog circuits, digital

logic, and I/O cells that must operate during the VAUX state. Each of the three power rails has an output terminal

for the external attachment of bypass capacitors to minimize circuit switching noise. These terminals are named

VDD_15_COMB, VDD_33_COMB, and VDD_33_COMBIO.

The recommended bypass capacitors for each combined output terminal are 1000 pF, 0.01 μF, and 1.0 μF.

When placing these capacitors on the bottom side of the circuit board, the smallest capacitor is positioned next

to the via associated with the combined output terminal and the largest capacitor is the most distant from the via.

The circuit board trace width connecting the combined output terminal via to the capacitors must be at least 12 to

15 mils wide with the trace length as short as possible.

Other than the three recommended capacitors, no external components or devices may be attached to these

combined output terminals.

9.2.1.1.3 Auxiliary Power

If VAUX power is available in the system, the XIO2001 has the VDD_33_AUX pin to support this feature. Without

fully understanding a system’s VAUX power distribution design, recommending external components for the

XIO2001 is difficult. At a minimum, a 0.1-μF bypass capacitor is placed near the XIO2001 and attached to the

system’s VAUX power supply. A robust design may include a Pi filter with bulk capacitors (5 μF to 100 μF) to

minimize voltage fluctuations. When the system is cycling main power or is in the VAUX state, the VDD_33_AUX

terminal requirements are that the input voltage cannot exceed 3.6 V or drop below 3.0 V for proper operation of

the bridge.

If VAUX power is not present within the system, this terminal is connected to VSS through a resistor with a value

greater than 3 k Ω.

9.2.1.1.4 VSS and VSSA Pins

For proper operation of the XIO2001, a unified VSS and VSSA ground plane is recommended. The circuit board

stack-up recommendation is to implement a layer two ground plane directly under the XIO2001 device. Both the

circuit board vias and ground trace widths that connect the VSS and VSSA ball pads to this ground plane must be

oversized to provide a low impedance connection.

9.2.1.1.5 Capacitor Selection Recommendations

When selecting bypass capacitors for the XIO2001 device, X7R-type capacitors are recommended. The

frequency versus impedance curves, quality, stability, and cost of these capacitors make them a logical choice

for most computer systems.

The selection of bulk capacitors with low-ESR specifications is recommended to minimize low-frequency power

supply noise. Today, the best low-ESR bulk capacitors are radial leaded aluminum electrolytic capacitors. These

capacitors typically have ESR specifications that are less than 0.01 Ω at 100 kHz. Also, several manufacturers

sell “ D ” size surface mount specialty polymer solid aluminum electrolytic capacitors with ESR specifications

slightly higher than 0.01 Ω at 100 kHz. Both of these bulk capacitor options significantly reduce low-frequency

power supply noise and ripple.

www.ti.com

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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