XIO2001IPNP datasheet(27/145 Pages) TI2

27 / 145 page

Table 8-1. XIO2001 Reset Options

RESET OPTION

XIO2001 FEATURE

RESET RESPONSE

Bridge internally-

generated

power-on reset

During a power-on cycle, the bridge asserts an internal reset

and monitors the VDD_15_COMB terminal. When this terminal

reaches 90% of the nominal input voltage specification,

power is considered stable. After stable power, the bridge

monitors the PCI Express reference clock (REFCLK) and

waits 10 μs after active clocks are detected. Then, internal

power-on reset is deasserted.

When the internal power-on reset is asserted, all control

registers, state machines, sticky register bits, and power

management state machines are initialized to their default

state.

In addition, the XIO2001 asserts the internal PCI bus

reset.

Global reset

input

GRST

When GRST is asserted low, an internal power-on reset

occurs. This reset is asynchronous and functions during

both normal power states and VAUX power states.

When GRST is asserted low, all control registers, state

machines, sticky register bits, and power management

state machines are initialized to their default state. In

addition, the bridge asserts PCI bus reset ( PRST). When

the rising edge of GRST occurs, the bridge samples the

state of all static control inputs and latches the information

internally. If an external serial EEPROM is detected, then a

download cycle is initiated. Also, the process to configure

and initialize the PCI Express link is started. The bridge

starts link training within 80 ms after GRST is deasserted.

PCI Express

reset input

PERST

This XIO2001 input terminal is used by an upstream PCI

Express device to generate a PCI Express reset and to

signal a system power good condition.

When PERST is asserted low, all control register bits that

are not sticky are reset. Within the configuration register

maps, the sticky bits are indicated by the

☆ symbol. Also,

all state machines that are not associated with sticky

functionality are reset.

When PERST is asserted low, the XIO2001 generates an

internal PCI Express reset as defined in the PCI Express

specification.

When PERST transitions from low to high, a system power

good condition is assumed by the XIO2001.

In addition, the XIO2001 asserts the internal PCI bus

reset.

Note: The system must assert PERST before power is

removed, before REFCLK is removed or before REFCLK

becomes unstable.

When the rising edge of PERST occurs, the XIO2001

samples the state of all static control inputs and latches

the information internally. If an external serial EEPROM is

detected, then a download cycle is initiated. Also, the

process to configure and initialize the PCI Express link is

started. The XIO2001 starts link training within 80 ms after

PERST is deasserted.

PCI Express

training control

hot reset

The XIO2001 responds to a training control hot reset

received on the PCI Express interface. After a training

control hot reset, the PCI Express interface enters the

DL_DOWN state.

In the DL_DOWN state, all remaining configuration register

bits and state machines are reset. All remaining bits

exclude sticky bits and EEPROM loadable bits. All

remaining state machines exclude sticky functionality and

EEPROM functionality.

Within the configuration register maps, the sticky bits are

indicated by the

☆ symbol and the EEPROM loadable bits

are indicated by the † symbol.

In addition, the XIO2001 asserts the internal PCI bus

reset.

PCI bus reset

PRST

System software has the ability to assert and deassert the

PRST terminal on the secondary PCI bus interface. This

terminal is the PCI bus reset.

When bit 6 (SRST) in the bridge control register at offset

3Eh (see Section 8.4.30) is asserted, the bridge asserts

the PRST terminal. A 0 in the SRST bit deasserts the

PRST terminal.

8.3.2 PCI Express Interface

The XIO2001 has an x1 PCI Express interface that runs at 2.5 Gb/s and is fully compliant to the PCI Express

Base Specification , Revision 2.0. The remainder of this section describes implementation considerations for the

XIO2001 primary PCI Express interface.

8.3.2.1 2.5-Gb/s Transmit and Receive Links

The XIO2001 TX and RX terminals attach to the upstream PCI Express device over a 2.5-Gb/s high- speed

differential transmit and receive PCI Express × 1 Link. The connection details are provided in Table 8-2.

www.ti.com

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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