XIO2001IPNP datasheet(61/145 Pages) TI2

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Table 8-28. Power Management Capabilities Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:11

PME_SUPPORT

PME support. This 5-bit field indicates the power states from which the bridge may assert

PME. Because the bridge never generates a PME except on a behalf of a secondary device,

this field is read-only and returns 00000b.

D2_SUPPORT

This bit returns a 1b when read, indicating that the function supports the D2 device power

state.

D1_SUPPORT

This bit returns a 1b when read, indicating that the function supports the D1 device power

state.

8:6

AUX_CURRENT

3.3 VAUX auxiliary current requirements. This field returns 000b since the bridge does not

generate PME from D3cold.

DSI

Device specific initialization. This bit returns 0b when read, indicating that the bridge does

not require special initialization beyond the standard PCI configuration header before a

generic class driver is able to use it.

RSVD

Reserved. Returns 0b when read.

PME_CLK

PME clock. This bit returns 0b indicating that the PCI clock is not needed to generate PME.

2:0

PM_VERSION

Power management version. If bit 26 (PCI_PM_VERSION_CTRL) in the general control

1.1 compatibility. If PCI_PM_VERSION_CTRL is 1b, then this field returns 011b indicating

revision 1.2 compatibility.

8.4.38 Power Management Control/Status Register

This register determines and changes the current power state of the bridge. No internal reset is generated when

transitioning from the D3hot state to the D0 state. See Table 8-29 for a complete description of the register

contents.

PCI register offset:

4Ch

Read-only, Read/Write

Default value:

0008h

BIT NUMBER

RESET STATE

Table 8-29. Power Management Control/Status Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

PME_STAT

PME status. This bit is read-only and returns 0b when read.

14:13

DATA_SCALE

Data scale. This 2-bit field returns 00b when read since the bridge does not use the data

12:9

DATA_SEL

Data select. This 4-bit field returns 0h when read since the bridge does not use the data

PME_EN

PME enable. This bit has no function and acts as scratchpad space. The default value for

this bit is 0b.

7:4

RSVD

Reserved. Returns 0h when read.

NO_SOFT_RESET

No soft reset. If bit 26 (PCI_PM_VERSION_CTRL) in the general control register (offset

D4h, see Section 8.4.66) is 0b, then this bit returns 0b for compatibility with version 1.1 of

the PCI Power Management Specification. If PCI_PM_VERSION_CTRL is 1b, then this bit

returns 1b indicating that no internal reset is generated and the device retains its

configuration context when transitioning from the D3hot state to the D0 state.

RSVD

Reserved. Returns 0b when read.

1:0

PWR_STATE

Power state. This 2-bit field determines the current power state of the function and sets the

function into a new power state. This field is encoded as follows:

00 = D0 (default)

01 = D1

10 = D2

11 = D3hot

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XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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