XIO2001IPNP datasheet(26/145 Pages) TI2

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8 Detailed Description

8.1 Overview

The Texas Instruments XIO2001 is a PCI Express to PCI local bus translation bridge that provides full PCI

Express and PCI local bus functionality and performance.

Power management (PM) features include active state link PM, PME mechanisms, the beacon and wake

protocols, and all conventional PCI D-states. If the active state link PM is enabled, then the link automatically

saves power when idle using the L0s and L1 states. PM active state NAK, PM PME, and PME-to-ACK

messages are supported. Standard PCI bus power management features provide several low power modes,

which enable the host system to further reduce power consumption.

The bridge has additional capabilities including, but not limited to, serial IRQ with MSI messages, serial

EEPROM, power override, clock run, PCI Express clock request and PCI bus LOCK. Also, five general-purpose

inputs and outputs (GPIOs) are provided for further system control and customization.

Robust pipeline architecture is implemented to minimize system latency across the bridge. If parity errors are

detected, then packet poisoning is supported for both upstream and downstream operations.

The PCI local bus is fully compliant with the PCI Local Bus Specification (Revision 2.3) and associated

programming model. Also, the bridge supports the standard PCI-to-PCI bridge programming model. The PCI bus

interface is 32-bit and can operate at either 25 MHz, 33 MHz, 50 MHz, or 66 MHz. Also, the PCI interface

provides fair arbitration and buffered clock outputs for up to 6 subordinate devices.

8.2 Functional Block Diagram

PCI Express

Transmitter

PCI Express

Receiver

PCI Bus Interface

Configuration and

Memory Register

GPIO

Serial

EEPROM

Serial

IRQ

Reset

Controller

Clock

Generator

Power

Mgmt

8.3 Feature Description

8.3.1 Bridge Reset Features

There are five bridge reset options that include internally-generated power-on reset, resets generated by

asserting input terminals, and software-initiated resets that are controlled by sending a PCI Express hot reset or

setting a configuration register bit. Table 8-1 identifies these reset sources and describes how the bridge

responds to each reset.

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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