XIO2001IPNP datasheet(117/145 Pages) TI2

117 / 145 page

• The PCLK66_SEL terminal determines if the XIO2001 provides either the standard 33/66 MHz frequencies or

25/50 MHz frequencies. If this terminal is pulled high at the de-assertion of PERST, then CLKOUTx terminals

provide the standard PCI 33/66 MHz frequencies (depending on the state of M66EN). If the terminal is pulled

low at the de-assertion of PERST, then a 25/50 MHz frequency is provided instead. The determination of

what frequency to use is design-specific, and this terminal must be pulled high or low appropriately.

• The M66EN terminal determines if the PCI Bus will operate at low speed (50/25 MHz) or high speed (66/33

MHz). At the de-assertion of PERST, the M66EN terminal is checked and if it is pulled to VCCP, then the high-

speed (66 MHz or 50 MHz) frequencies are used. If the pin is low, then the low-speed (33 MHz or 25 MHz)

frequencies are used. If the speed of all devices attached to the PCI bus is known, then this terminal can be

pulled appropriately to set the speed of the PCI bus. If add-in card slots are present on a high-speed bus that

may have low speed devices attached, then the terminal can be pulled high and connected to the slot,

permitting the add-in card to pull the terminal low and reduce the bus speed if a low-speed card is inserted.

• IDSEL for each PCI bus device must be resistively coupled (100 Ω) to one of the address lines between

AD31 and AD16. Please refer to the XIO2001 Data Manual for the configuration register transaction device

number to AD bit translation chart.

• PCI interrupts can be routed to the INT[D:A] inputs on the XIO2001. These four inputs are asynchronous to

the PCI bus clock and will detect state changes even if the PCI bus clock is stopped. For each INT[D:A] input,

an approved PCI bus pullup resistor to VCCP is required to keep each interrupt signal from floating. Interrupts

on the XIO2001 that are not connected to any device may be tied together and pulled-up through a single

resistor.

• PRST is a required PCI bus signal and must be connected to all devices. This output signal is asynchronous

to the PCI bus clock. Since the output driver is always enabled and either driving high or low, no pullup

resistor is needed.

• LOCK is an optional PCI bus signal. If LOCK is present in a system, it is connected to each PCI bus device

that supports the feature and must meet PCI bus loading requirements for the selected clock frequency. An

approved PCI bus pullup resistor to VCCP is required to keep this signal from floating, even if it is not

connected to devices on the bus. LOCK is a bused signal and synchronous to the PCI bus clock. All

synchronous PCI bus signals must be length matched to meet clock setup and hold requirements.

• SERIRQ is an optional PCI bus signal. When PERST is de-asserted, if a pullup resistor to VCCP is detected

on terminal M08, the serial IRQ interface is enabled. A pulldown resistor to V SS disables this feature. If

SERIRQ is present in a system, it is connected to each PCI bus device that supports the feature and must

meet PCI bus loading requirements for the selected clock frequency. An approved PCI bus pullup resistor to

VCCP is required to keep this signal from floating. SERIRQ is a bused signal and synchronous to the PCI bus

clock. All synchronous PCI bus signals must be length matched to meet clock setup and hold requirements.

Note

SERIRQ does not support serialized PCI interrupts and is used for serializing the 16 ISA interrupts.

• CLKRUN is an optional PCI bus signal that is shared with the GPIO0 pin. When PERST is de-asserted and if

a pullup resistor to VDD_33 is detected on pin C11 (CLKRUN_EN), the clock run feature is enabled. If

CLKRUN is required in a system, this pin is connected to each PCI bus device and must meet PCI bus

loading requirements for the selected clock frequency. An approved PCI bus pullup resistor to VDD_33 is

required per the PCI Mobile Design Guide . CLKRUN is a bused signal and synchronous to the PCI bus

clock. All synchronous PCI bus signals must be length matched to meet clock setup and hold requirements.

Note

If CLKRUN is used in a system, it must be supported by all devices attached to the PCI bus; if a

device that does not support CLKRUN is attached to a bus where it is enabled, there is a danger

that it will not be able to have a clock when it requires one.

• PWR_OVRD is an optional PCI bus signal that is shared with the GPIO1 terminal. In PWR_OVRD mode, this

pin is always an output and is asynchronous to the PCI bus clock. When the power override control bits in the

general control register at offset D4h are set to 001b or 011b, the M09 pin operates as the PWR_OVRD

signal. Prior to setting the power override control bits, the GPIO1 // PWR_OVRD pin defaults to a standard

GPIO pin.

www.ti.com

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

Submit Document Feedback

117

Product Folder Links: XIO2001

XIO2001IPNP датащи(PDF) 117 Page - Texas Instruments

XIO2001IPNP датащи(HTML) 117 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL