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XIO2001IPNP датащи(PDF) 85 Page - Texas Instruments

номер детали XIO2001IPNP
подробное описание детали  XIO2001 PCI Express to PCI Bus Translation Bridge
PDF  145 Pages
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XIO2001IPNP датащи(HTML) 85 Page - Texas Instruments

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8.4.72 Arbiter Time-Out Status Register
The arbiter time-out status register contains the status of each request (request 5–0) time-out. The time-out
status bit for the respective request is set if the device did not assert FRAME after the arbiter time-out value. See
Table 8-55 for a complete description of the register contents.
PCI register offset:
DEh
Register type:
Read/Clear
Default value:
00h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
Table 8-55. Arbiter Time-Out Status Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
7:6
RSVD
R
Reserved. Returns 00b when read.
5
REQ5_TO
RCU
Request 5 Time Out Status
0 =
1 =
No time-out
Time-out has occurred
4
REQ4_TO
RCU
Request 4 Time Out Status
0 =
1 =
No time-out
Time-out has occurred
3
REQ3_TO
RCU
Request 3 Time Out Status
0 =
1 =
No time-out
Time-out has occurred
2
REQ2_TO
RCU
Request 2 Time Out Status
0 =
1 =
No time-out
Time-out has occurred
1
REQ1_TO
RCU
Request 1Time Out Status
0 =
1 =
No time-out
Time-out has occurred
0
REQ0_TO
RCU
Request 0 Time Out Status
0 =
1 =
No time-out
Time-out has occurred
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XIO2001
SCPS212J – MAY 2009 – REVISED JANUARY 2021
Copyright © 2021 Texas Instruments Incorporated
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