XIO2001IPNP datasheet(118/145 Pages) TI2

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• PME is an optional PCI bus input terminal to detect power management events from downstream devices.

The PME terminal is operational during both main power states and VAUX states. The PME receiver has

hysteresis and expects an asynchronous input signal. The board design requirements associated with this

PME terminal are the same whether or not the terminal is connected to a downstream device. If the system

includes a VAUX supply, the PME terminal requires a weak pullup resistor connected to VAUX to keep the

terminal from floating. If no VAUX supply is present, the pullup resistor is connected to VDD_33.

• The bridge supports external PCI bus clock sources. If an external clock is a system requirement, the

external clock source is connected to the CLK terminal. The trace length relationship between the

synchronous bus signals and the external clock signals that is previously described is still required to meet

PCI bus setup and hold. For external clock mode, all seven CLKOUT[6:0] terminals can be disabled using the

clock control register at offset D8h. Plus, the XIO2001 clock run feature must be disabled with external PCI

bus clocks because there is no method of turning off external clocks.

Note

If an external clock with a frequency higher than 33 MHz is used, the M66EN terminal must be

pulled up for the XIO2001 to function correctly.

• The XIO2001 supports an external PCI bus arbiter. When PERST is deasserted, the logic state of the

EXT_ARB_EN pin is checked. If an external arbiter is required, EXT_ARB_EN is connected to VDD_33. When

connecting the XIO2001 to an external arbiter, the external arbiter’s REQ signal is connected to the XIO2001

0 GNT output terminal. Likewise, the GNT signal from the external arbiter is connected to the XIO2001 0

REQ input pin. Unused REQ signals on the XIO2001 should be tied together and connected to VCCP through

a pull-up resistor. When in external arbiter mode, all internal XIO2001 port arbitration features are disabled.

Figure 9-3 illustrates the connectivity of an external arbiter.

XIO2001

EXT_ARB_EN

REQ[5:1]

GNT0

REQ0

VCCP

3.3 V

GNTx

GNTy

REQx

REQy

External Arbiter

GNT

REQ

PCI Device

PCI Bus

Figure 9-3. External Arbiter Connections

9.2.1.2.1.1 Bus Parking

Because of the shared bus nature of PCI, it is required that if the bus is idle at a given time that some device on

the bus must drive some signals to stable states. These signals are the address/data lines, the command/byte

enables, and a valid parity. If no devices are requesting use of the bus, it is the responsibility of the arbiter to

assign ownership of the bus so that the bus signals are never floating while in idle states.

If the XIO2001 internal arbiter is enabled then there are two modes supported for bus parking. The default mode

for bus parking is for the arbiter to continue to assert GNT for the last bus master. In this mode once a device

has completed its transaction, the arbiter will continue to assert the GNT for that bus master and that device is

required to drive a stable pattern onto the required signals. This will continue until another device requests use

of the bus resulting in the arbiter removing GNT from the current bus owner grants it to the new requestor.

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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