XIO2001IPNP datasheet(42/145 Pages) TI2

42 / 145 page

8.4 Register Maps

8.4.1 Classic PCI Configuration Space

The programming model of the XIO2001 PCI-Express to PCI bridge is compliant to the classic PCI-to-PCI bridge

programming model. The PCI configuration map uses the type 1 PCI bridge header.

All bits marked with a are sticky bits and are reset by a global reset ( GRST) or the internally-generated power-

on reset. All bits marked with a

☆ are reset by a PCI Express reset ( PERST), a GRST, or the internally-

generated power-on reset. The remaining register bits are reset by a PCI Express hot reset, PERST, GRST, or

the internally-generated power-on reset.

Table 8-11. Classic PCI Configuration Register Map

OFFSET

Device ID

Vendor ID

000h

Status

Command

004h

Class code

Revision ID

008h

BIST

Header type

Latency timer

Cache line size

00Ch

Device control base address

010h

Reserved

014h

Secondary latency timer

Subordinate bus number

Secondary bus number

Primary bus number

018h

Secondary status

I/O limit

I/O base

01Ch

Memory limit

Memory base

020h

Prefetchable memory limit

Prefetchable memory base

024h

Prefetchable base upper 32 bits

028h

Prefetchable limit upper 32 bits

02Ch

I/O limit upper 16 bits

I/O base upper 16 bits

030h

Reserved

Capabilities pointer

034h

Expansion ROM base address

038h

Bridge control

Interrupt pin

Interrupt line

03Ch

Reserved

Next item pointer

SSID/SSVID CAP ID

040h

Subsystem ID(1)

Subsystem vendor ID(1)

044h

Power management capabilities

Next item pointer

PM CAP ID

048h

PM Data

PMCSR_BSE

Power management CSR

04Ch

MSI message control

Next item pointer

MSI CAP ID

050h

MSI message address

054h

MSI upper message address

058h

Reserved

MSI message data

05Ch

MSI Mask Bits Register

060h

MSI Pending Bits Register

064h

Reserved

068h–06Ch

PCI Express capabilities register

Next item pointer

PCI Express capability ID

070h

Device Capabilities

074h

Device status

Device control

078h

Link Capabilities

07Ch

Link status

Link control

080h

Slot Capabilities

084h

Slot Status

Slot Control

088h

Root Capabilities

Root Control

08Ch

Root Status

090h

Device Capabilities 2

094h

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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