XIO2001IPNP datasheet(50/145 Pages) TI2

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8.4.15 Secondary Latency Timer Register

This read/write register specifies the secondary bus latency timer for the bridge, in units of PCI clock cycles.

PCI register offset:

1Bh

Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

8.4.16 I/O Base Register

This read/write register specifies the lower limit of the I/O addresses that the bridge forwards downstream. See

Table 8-16 for a complete description of the register contents.

PCI register offset:

1Ch

Read-only, Read/Write

Default value:

01h

BIT NUMBER

RESET STATE

Table 8-16. I/O Base Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

7:4

IOBASE

I/O base. Defines the bottom address of the I/O address range that determines when to forward

I/O transactions from one interface to the other. These bits correspond to address bits [15:12] in

the I/O address. The lower 12 bits are assumed to be 000h. The 16 bits corresponding to address

bits [31:16] of the I/O address are defined in the I/O base upper 16 bits register (offset 30h, see

Section 8.4.25).

3:0

IOTYPE

I/O type. This field is read-only 1h indicating that the bridge supports 32-bit I/O addressing.

8.4.17 I/O Limit Register

This read/write register specifies the upper limit of the I/O addresses that the bridge forwards downstream. See

Table 8-17 for a complete description of the register contents.

PCI register offset:

1Dh

Read-only, Read/Write

Default value:

01h

BIT NUMBER

RESET STATE

Table 8-17. I/O Limit Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

7:4

IOLIMIT

I/O limit. Defines the top address of the I/O address range that determines when to forward I/O

transactions from one interface to the other. These bits correspond to address bits [15:12] in the

I/O address. The lower 12 bits are assumed to be FFFh. The 16 bits corresponding to address bits

[31:16] of the I/O address are defined in the I/O limit upper 16 bits register (offset 32h, see Section

8.4.26).

3:0

IOTYPE

I/O type. This field is read-only 1h indicating that the bridge supports 32-bit I/O addressing.

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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