XIO2001IPNP datasheet(112/145 Pages) TI2

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8.6.13 Cache Timer Transfer Limit Register

This register is used to set the number of PCI cycle starts that have to occur without a read hit on the completion

data buffer, before the cache data can be discarded. This register is an alias for the pre-fetch agent request

limits register in the classic PCI configuration space (offset EAh, see Section 8.4.77). See Table 8-83 for a

complete description of the register contents.

Device control memory window register offset:

52h

Read/Clear

Default value:

0008h

BIT NUMBER

RESET STATE

Table 8-83. Cache Timer Transfer Limit Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:8

RSVD

Reserved. Returns 00h when read.

7:0(1)

CACHE_TMR_XFR

_LIMIT

Number of PCI cycle starts that have to occur without a read hit on the completion data

buffer, before the cache data can be discarded.

(1)

These bits are reset by a PCI Express reset ( PERST), a GRST, or the internally-generated power-on reset.

8.6.14 Cache Timer Lower Limit Register

Minimum number of clock cycles that must have passed without a read hit on the completion data buffer before

the "cache miss limit" check can be triggered. See Table 8-84 for a complete description of the register contents.

Device control memory window register offset:

54h

Read/Clear

Default value:

007Fh

BIT NUMBER

RESET STATE

Table 8-84. Cache Timer Lower Limit Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:12

RSVD

Reserved. Returns 0h when read.

11:0(1)

CACHE_TIMER

_LOWER_LIMIT

Minimum number of clock cycles that must have passed without a read hit on the

completion data buffer before the "cache miss limit" check can be triggered.

(1)

These bits are reset by a PCI Express reset ( PERST), a GRST, or the internally-generated power-on reset.

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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