XIO2001IPNP datasheet(84/145 Pages) TI2

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8.4.71 Arbiter Request Mask Register

The arbiter request mask register enables and disables support for requests from specific masters on the

secondary bus. The arbiter request mask register also controls if a request input is automatically masked on an

arbiter time-out. See Table 8-54 for a complete description of the register contents.

PCI register offset:

DDh

Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

Table 8-54. Arbiter Request Mask Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

7(1)

ARB_TIMEOUT

Arbiter time-out. This bit enables the arbiter time-out feature. The arbiter time-out is defined

as the number of PCI clocks after the PCI bus has gone idle for a device to assert FRAME

before the arbiter assumes the device will not respond.

0 = Arbiter time disabled (default)

1 = Arbiter time-out set to 16 PCI clocks

6(1)

AUTO_MASK

Automatic request mask. This bit enables automatic request masking when an arbiter time-

out occurs.

0 = Automatic request masking disabled (default)

1 = Automatic request masking enabled

5(1)

REQ5_MASK

Request 5 ( REQ5) Mask. Setting this bit forces the internal arbiter to ignore requests

signal on request input 0.

0 = Use request 5 (default)

1 = Ignore request 5

4(1)

REQ4_MASK

Request 4 ( REQ4) Mask. Setting this bit forces the internal arbiter to ignore requests

signal on request input 0.

0 = Use request 4 (default)

1 = Ignore request 4

3(1)

REQ3_MASK

Request 3 ( REQ3) Mask. Setting this bit forces the internal arbiter to ignore requests

signal on request input 0.

0 = Use request 3 (default)

1 = Ignore request 3

2(1)

REQ2_MASK

Request 2 ( REQ2) Mask. Setting this bit forces the internal arbiter to ignore requests

signal on request input 0.

0 = Use request 2 (default)

1 = Ignore request 2

1(1)

REQ1_MASK

Request 1 ( REQ1) Mask. Setting this bit forces the internal arbiter to ignore requests

signal on request input 0.

0 = Use request 2 (default)

1 = Ignore request 2

0(1)

REQ0_MASK

Request 0 ( REQ0) Mask. Setting this bit forces the internal arbiter to ignore requests

signal on request input 0.

0 = Use request 0 (default)

1 = Ignore request 0

(1)

These bits are reset by a PCI Express reset ( PERST), a GRST, or the internally-generated power-on reset.

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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