XIO2001IPNP datasheet(14/145 Pages) TI2

14 / 145 page

Miscellaneous Pins (continued)

SIGNAL

ZWS

BALL

NO.

ZAJ

BALL

NO.

PNP

PIN NO.

I/O

TYPE

CELL

TYPE

CLAMP

RAIL

EXTERNAL

PARTS

DESCRIPTION

GPIO4 // SCL

M10

I/O

CMOS

VDD_33

Optional

pullup resistor

GPIO4 or serial-bus clock. This terminal

functions as serial-bus clock if a pullup

resistor is detected on SCL or when the

SBDETECT bit is set in the Serial Bus

Control and Status Register (see

Section 8.4.59). If no pullup is detected

then this terminal functions as GPIO4.

Note: In serial-bus mode, an external

pullup resistor is required to prevent the

SCL signal from floating.

Note: This terminal has an internal

active pullup resistor. The pullup is only

active when reset is asserted or when

the GPIO is configured as an input.

GRST

N13

M11

CMOS

VDD_33

_COMBIO

–

Global reset input. Asynchronously

resets all logic in device, including sticky

bits and power management state

machines.

Note: The GRST input buffer has both

hysteresis and an internal active pullup.

The pullup is active at all times.

PCLK66_

SEL

B12

A11

CMOS

VDD_33

Optional

pulldown

resistor

PCI clock select. This terminal

determines the default PCI clock

frequency driven out the CLKOUTx

terminals.

0 = 50 MHz PCI Clock

1 = 66 MHz PCI Clock

Note: This terminal has an internal

active pullup resistor. This pullup is

active at all times.

Note: M66EN terminal also has an affect

of PCI clock frequency.

SERIRQ

N08

M08

I/O

PCI

Bus

PCIR

Pullup or

pulldown

resistor

Serial IRQ interface. This terminal

functions as a serial IRQ interface if a

pullup is detected when PERST is

deasserted. If a pulldown is detected,

then the serial IRQ interface is disabled.

VREG_

PD33

D12

E11

CMOS

VDD_33

_COMBIO

Pulldown

resistor

3.3-V voltage regulator powerdown. This

terminal should always be tied directly to

ground or an optional pulldown resistor

can be used.

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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