XIO2001IPNP datasheet(96/145 Pages) TI2

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8.5.7 Correctable Error Mask Register

The correctable error mask register controls the reporting of individual errors as they occur. When a mask bit is

set to 1b, the corresponding error status bit is not set, PCI Express error messages are blocked, the header log

is not loaded, and the first error pointer is not updated. See Table 8-68 for a complete description of the register

contents.

PCI Express extended register offset:

114h

Read-only, Read/Write

Default value:

0000 2000h

BIT NUMBER

RESET STATE

BIT NUMBER

RESET STATE

Table 8-68. Correctable Error Mask Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:14 RSVD

Reserved. Returns 000 0000 0000 0000 0000b when read.

13(1)

ANFEM

Advisory Non-Fatal Error Mask.

0 = Error condition is unmasked

1 = Error condition is masked (default)

12(1)

REPLAY_TMOUT_MASK

Replay timer time-out mask.

0 = Error condition is unmasked (default)

1 = Error condition is masked

11:9

RSVD

Reserved. Returns 000b when read.

8(1)

REPLAY_ROLL_MASK

REPLAY_NUM rollover mask.

0 = Error condition is unmasked (default)

1 = Error condition is masked

7(1)

BAD_DLLP_MASK

Bad DLLP error mask.

0 = Error condition is unmasked (default)

1 = Error condition is masked

6(1)

BAD_TLP_MASK

Bad TLP error mask.

0 = Error condition is unmasked (default)

1 = Error condition is masked

5:1

RSVD

Reserved. Returns 00000b when read.

0(1)

RX_ERROR_MASK

Receiver error mask.

0 = Error condition is unmasked (default)

1 = Error condition is masked

(1)

These bits are reset by a PCI Express reset ( PERST), a GRST, or the internally-generated power-on reset.

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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