XIO2001IPNP datasheet(34/145 Pages) TI2

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8.3.7 PCI Express to PCI Bus Lock Conversion

The bus-locking protocol defined in the PCI Express Base Specification and PCI Local Bus Specification is

provided on the bridge as an additional compatibility feature. The PCI bus LOCK signal is a dedicated output

that is enabled by setting bit 12 in the general control register at offset D4h. See Section 8.4.66, for details.

Note

The use of LOCK is only supported by PCI-Express to PCI Bridges in the downstream direction (away

from the root complex).

PCI Express locked-memory read request transactions are treated the same as PCI Express memory read

transactions except that the bridge returns a completion for a locked-memory read. Also, the bridge uses the PCI

LOCK protocol when initiating the memory read transaction on the PCI bus.

When a PCI Express locked-memory read request transaction is received and the bridge is not already locked,

the bridge arbitrates for use of the LOCK terminal by asserting REQ. If the bridge receives GNT and the LOCK

terminal is high, then the bridge drives the LOCK terminal low after the address phase of the first locked-memory

read transaction to take ownership of LOCK. The bridge continues to assert LOCK except during the address

phase of locked transactions. If the bridge receives GNT and the LOCK terminal is low, then the bridge

deasserts its REQ and waits until LOCK is high and the bus is idle before re-arbitrating for the use of LOCK.

Data

Address

CLK

FRAME

LOCK

IRDY

TRDY

DEVSEL

Figure 8-6. Starting a Locked Sequence

Once the bridge has ownership of LOCK, the bridge initiates the lock read as a memory read transaction on the

PCI bus. When the target of the locked-memory read returns data, the bridge is considered locked and all

transactions not associated with the locked sequence are blocked by the bridge.

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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