XIO2001IPNP datasheet(114/145 Pages) TI2

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9 Application, Implementation, and Layout

9.1 Application Information

shows a typical implementation of the XIO2001 PCI Express (PCIe) to PCI translation bridge. The device serves

as a bridge between an upstream PCIe device and up to six downstream PCI bus devices. The XIO2001

operates only with the PCIe interface as the primary bus and the PCI bus interface as the secondary bus. The

PCI bus interface is 32 bits wide and the XIO2001 can be set to provide a PCI clock that operates at 25 MHz, 33

MHz, 50 MHz, or 66 MHz.

9.2 Typical Application

9.2.1 In-Card Implementation

Figure 9-1. Typical Application

A common application for the XIO2001 is a PCIe-to-PCI bridge add-in card which implements a peripheral

component interconnect (PCI) express to PCI bridge circuit using the Texas Instruments XIO2001 PCI Express

to PCI Bus Translation Bridge. Designed as an ×1 add-in card, it is routed on FR4 as a 8-layer (4 signals, 2

power, and 2 ground) board with a 100-Ω differential impedance (50-Ω single-ended) using standard routing

guidelines and requirements.

9.2.1.1 Design Requirements

9.2.1.1.1 VCCP Clamping Rail

The XIO2001 has a PCI bus I/O clamp rail (PCIR) that can be either 3.3 V or 5 V, depending on the system

implementation. For 25-MHz or 33-MHz PCI bus implementations, PCIR may be connected to either 3.3 V or 5.0

V. For 50-MHz or 66-MHz PCI bus implementations, a 3.3-V connection is the only approved configuration. The

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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