XIO2001IPNP datasheet(88/145 Pages) TI2

88 / 145 page

Table 8-58. Serial IRQ Status Register Description (continued)

BIT

FIELD NAME

ACCESS

DESCRIPTION

13(1)

IRQ13

RCU

IRQ 13 asserted. This bit indicates that the IRQ13 has been asserted.

0 = Deasserted

1 = Asserted

12(1)

IRQ12

RCU

IRQ 12 asserted. This bit indicates that the IRQ12 has been asserted.

0 = Deasserted

1 = Asserted

11(1)

IRQ11

RCU

IRQ 11 asserted. This bit indicates that the IRQ11 has been asserted.

0 = Deasserted

1 = Asserted

10(1)

IRQ10

RCU

IRQ 10 asserted. This bit indicates that the IRQ10 has been asserted.

0 = Deasserted

1 = Asserted

9(1)

IRQ9

RCU

IRQ 9 asserted. This bit indicates that the IRQ9 has been asserted.

0 = Deasserted

1 = Asserted

8(1)

IRQ8

RCU

IRQ 8 asserted. This bit indicates that the IRQ8 has been asserted.

0 = Deasserted

1 = Asserted

7(1)

IRQ7

RCU

IRQ 7 asserted. This bit indicates that the IRQ7 has been asserted.

0 = Deasserted

1 = Asserted

6(1)

IRQ6

RCU

IRQ 6 asserted. This bit indicates that the IRQ6 has been asserted.

0 = Deasserted

1 = Asserted

5(1)

IRQ5

RCU

IRQ 5 asserted. This bit indicates that the IRQ5 has been asserted.

0 = Deasserted

1 = Asserted

4(1)

IRQ4

RCU

IRQ 4 asserted. This bit indicates that the IRQ4 has been asserted.

0 = Deasserted

1 = Asserted

3(1)

IRQ3

RCU

IRQ 3 asserted. This bit indicates that the IRQ3 has been asserted.

0 = Deasserted

1 = Asserted

2(1)

IRQ2

RCU

IRQ 2 asserted. This bit indicates that the IRQ2 has been asserted.

0 = Deasserted

1 = Asserted

1(1)

IRQ1

RCU

IRQ 1 asserted. This bit indicates that the IRQ1 has been asserted.

0 = Deasserted

1 = Asserted

0(1)

IRQ0

RCU

IRQ 0 asserted. This bit indicates that the IRQ0 has been asserted.

0 = Deasserted

1 = Asserted

(1)

These bits are reset by a PCI Express reset ( PERST), a GRST, or the internally-generated power-on reset.

8.4.76 Pre-Fetch Agent Request Limits Register

This register is used to set the Pre-Fetch Agent's limits on retrieving data using upstream reads. See Table 8-59

for a complete description of the register contents.

PCI register offset:

E8h

Read/Clear

Default value:

0443h

BIT NUMBER

RESET STATE

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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