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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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XIO2001IPNP датащи(PDF) 99 Page - Texas Instruments |
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XIO2001IPNP датащи(HTML) 99 Page - Texas Instruments |
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99 / 145 page  Register type: Read-only, Read/Write Default value: 0000 1340h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 1 0 0 1 1 0 1 0 0 0 0 0 0 Table 8-71. Secondary Uncorrectable Error Severity Register Description BIT FIELD NAME ACCESS DESCRIPTION 31:14 RSVD R Reserved. Returns 00 0000 0000 0000 0000b when read. 13(1) INTERNAL_ERROR_SEVR RW Internal bridge error. This severity bit is associated with a PCI-X error and has no effect on the bridge. 12(1) SERR_DETECT_SEVR RW SERR assertion detected 0 = Error condition is signaled using ERR_NONFATAL 1 = Error condition is signaled using ERR_FATAL (default) 11(1) PERR_DETECT_SEVR RW PERR assertion detected 0 = Error condition is signaled using ERR_NONFATAL (default) 1 = Error condition is signaled using ERR_FATAL 10(1) DISCARD_TIMER_SEVR RW Delayed transaction discard timer expired 0 = Error condition is signaled using ERR_NONFATAL (default) 1 = Error condition is signaled using ERR_FATAL 9(1) UNCOR_ADDR_SEVR RW Uncorrectable address error 0 = Error condition is signaled using ERR_NONFATAL 1 = Error condition is signaled using ERR_FATAL (default) 8(1) UNCOR_ATTRIB_SEVR RW Uncorrectable attribute error. This severity bit is associated with a PCI-X error and has no effect on the bridge. 7(1) UNCOR_DATA_SEVR RW Uncorrectable data error 0 = Error condition is signaled using ERR_NONFATAL (default) 1 = Error condition is signaled using ERR_FATAL 6(1) UNCOR_SPLTMSG_SEVR RW Uncorrectable split completion message data error. This severity bit is associated with a PCI-X error and has no effect on the bridge. 5(1) UNCOR_SPLTCMP_SEVR RW Unexpected split completion error. This severity bit is associated with a PCI-X error and has no effect on the bridge. 4 RSVD R Reserved. Returns 0b when read. 3(1) MASTER_ABORT_SEVR RW Received master abort 0 = Error condition is signaled using ERR_NONFATAL (default) 1 = Error condition is signaled using ERR_FATAL 2(1) TARGET_ABORT_SEVR RW Received target aborta 0 = Error condition is signaled using ERR_NONFATAL (default) 1 = Error condition is signaled using ERR_FATAL 1(1) MABRT_SPLIT_SEVR RW Master abort on split completion. This severity bit is associated with a PCI-X error and has no effect on the bridge. 0 TABRT_SPLIT_SEVR R Target abort on split completion. This severity bit is associated with a PCI-X error and has no effect on the bridge. (1) These bits are reset by a PCI Express reset ( PERST), a GRST, or the internally-generated power-on reset. www.ti.com XIO2001 SCPS212J – MAY 2009 – REVISED JANUARY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 99 Product Folder Links: XIO2001 |
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