XIO2001IPNP datasheet(19/145 Pages) TI2

19 / 145 page

PARAMETER

TERMINALS

MIN

NOM

MAX

UNIT

COMMENTS

ZRX-HIGH-IMP-DC-POS (7)

DC input CM input impedance for V > 0

during reset or powerdown

RXP, RXN

kΩ

Rx DC CM impedance with the Rx terminations not

powered, measured over the range 0 to 200 mV with

respect to ground.

ZRX-HIGH-IMP-DC-NEG (7)

DC input CM input impedance for V > 0

during reset or powerdown

RXP, RXN

kΩ

Rx DC CM impedance with the Rx terminations not

powered, measured over the range 0 to 200 mV with

respect to ground.

VRX-IDLE-DET-DIFFp-p

Electrical idle detect threshold

RXP, RXN

175

VRX-IDLE-DET-DIFFp-p = 2*|VRXP – VRXN| measured at the

receiver package terminals

TRX-IDLE-DET-DIFF-ENTER-TIME

Unexpected electrical idle enter detect

threshold integration time

RXP, RXN

An unexpected electrical idle (VRX-DIFFp-p < VRX-IDLE-

DET-DIFFp-p) must be recognized no longer than TRX-IDLE-

DET-DIFF-ENTER-TIME to signal an unexpected idle

condition.

(1)

No test load is necessarily associated with this value.

(2)

Specified at the measurement point and measured over any 250 consecutive UIs. A test load must be used as the RX device when

taking measurements. If the clocks to the RX and TX are not derived from the same reference clock, then the TX UI recovered from

3500 consecutive UIs is used as a reference for the eye diagram.

(3)

A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and interconnect

collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the

median and the maximum deviation from the median is less than half of the total UI jitter budget collected over any 250 consecutive TX

UIs. It must be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of

jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the RX and TX are not derived

from the same reference clock, then the TX UI recovered from 3500 consecutive UIs must be used as the reference for the eye

diagram.

(4)

The receiver input impedance results in a differential return loss greater than or equal to 15 dB with the P line biased to 300 mV and

the N line biased to .300 mV and a common mode return loss greater than or equal to 6 dB (no bias required) over a frequency range

of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference impedance for return loss

measurements for is 50 . to ground for both the P and N line (i.e., as measured by a Vector Network Analyzer with 50-. probes). The

series capacitors CTX is optional for the return loss measurement.

(5)

Impedance during all link training status state machine (LTSSM) states. When transitioning from a PCI Express reset to the detect

state (the initial state of the LTSSM) there is a 5-ms transition time before receiver termination values must be met on the unconfigured

lane of a port.

(6)

A single PLL bandwidth and peaking value of 1.5 to 22 MHz and 3 dB are defined.

(7)

ZRX-HIGH-IMP-DC-NEG and ZRX-HIGH-IMP-DC-POS are defined respectively for negative and postive voltages at the input of the receiver.

6.8 PCI Express Differential Reference Clock Input Ranges (1)

PARAMETER

TERMINALS

MIN

NOM

MAX

UNIT

COMMENTS

fIN-DIFF

Differential input frequency

REFCLK+

REFCLK–

100

MHz

The input frequency is 100 MHz + 300 ppm and –2800

ppm including SSC-dictated variations.

fIN-SE

Single-ended input frequency

REFCLK+

125

MHz

The input frequency is 125 MHz + 300 ppm and –300

ppm.

VRX-DIFFp-p

Differential input peak-to-

peak voltage

REFCLK+

REFCLK–

0.175

1.2

VRX-DIFFp-p = 2*|VREFCLK+ – VREFCLK-|

VIH-SE

REFCLK+

0.7 VDDA_33

VDDA_33

Single-ended, reference clock mode high-level input

voltage

VIL-SE

REFCLK+

0.3 VDDA_33

Single-ended, reference clock mode low-level input

voltage

VRX-CM-ACp

AC peak common mode input

voltage

REFCLK+

REFCLK–

140

VRX-CM-ACp = RMS(|VREFCLK+ + VREFCLK-|/2 VRX-CM-DC)

VRX-CM-DC = DC(avg) of

|VREFCLK+ + VREFCLK-|/2

Duty cycle

REFCLK+

REFCLK–

40%

60%

Differential and single-ended waveform input duty

cycle

ZC-DC

Clock source DC impedance

REFCLK+

REFCLK–

Ω

REFCLK± dc differential mode impedance

ZRX-DC

DC input impedance

REFCLK+

REFCLK–

kΩ

REFCLK+ dc single-ended mode impedance

(1)

The XIO2001 is compliant with the defined system jitter models for a PCI-Express reference clock and associated TX/RX link. Any

usage of the XIO2001 in a system configuration that does not conform to the defined system jitter models requires the system designer

to validate the system jitter budgets.

www.ti.com

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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