XIO2001IPNP datasheet(119/145 Pages) TI2

119 / 145 page

Alternatively, the XIO2001 can be configured to self-park. In this mode if no other devices have their REQ

asserted, the XIO2001 will remove GNT from the current bus owner and drive a stable pattern onto the required

lines.

It is suggested that implementations use the default mode of bus parking. The PCI Specification recommends

leaving the current GNT signal asserted if no devices are asserting REQ. Some PCI bus masters will release

their REQ signals after having begun a transaction, even if that transaction may require the use of the bus for an

extended time. If the XIO2001 self-parks the bus, then these bus masters will have their transaction lengths

limited to the latency timer setting. This may result in increased arbitration, higher overhead for transactions, and

decreased bus performance.

9.2.1.2.1.2 I/O Characteristics

Figure 9-4 shows a 3-state bi-directional buffer that represents the I/O cell design for the PCI bus. Section 6.9,

Electrical Characteristics over Recommended Operating Conditions, provides the electrical characteristics of the

PCI bus I/O cell.

Note

The PCI bus interface on the bridge meets the ac specifications of the PCI Local Bus Specification.

Additionally, PCI bus terminals (input or I/O) must be held high or low to prevent them from floating.

PCIR

Figure 9-4. 3-State Bidirectional Buffer

9.2.1.2.1.3 Clamping Voltage

In the bridge, the PCI bus I/O drivers are powered from the VDD_33 power rail. Plus, the I/O driver cell is tolerant

to input signals with 5-V peak-to-peak amplitudes.

For PCI bus interfaces operating at 50 MHz or 66 MHz, all devices are required to output only 3.3-V peak-to-

peak signal amplitudes. For PCI bus interfaces operating at 25-MHz or 33-MHz, devices may output either 3.3-V

or 5-V peak-to-peak signal amplitudes. The bridge accommodates both signal amplitudes.

Each PCI bus I/O driver cell has a clamping diode connected to the internal VCCP voltage rail that protects the

cell from excessive input voltage. The internal VCCP rail is connected to two PCIR terminals. If the PCI signaling

is 3.3-V, then PCIR terminals are connected to a 3.3-V power supply via a 1-kΩ resistor. If the PCI signaling is 5-

V, then the PCIR terminals are connected to a 5-V power supply via a 1kΩ resistor.

The PCI bus signals attached to the VCCP clamping voltage are identified as follows

• Pin Functions table, PCI System Terminals, all terminal names except for PME

• Pin Functions table, Miscellaneous Terminals, the terminal name SERIRQ.

9.2.1.2.1.4 PCI Bus Clock Run

The bridge supports the clock run protocol as specified in the PCI Mobile Design Guide. When the clock run

protocol is enabled, the bridge assumes the role of the central resource master.

To enable the clock run function, terminal CLKRUN_EN is asserted high. Then, terminal GPIO0 is enabled as

the CLKRUN signal. An external pullup resistor must be provided to prevent the CLKRUN signal from floating To

verify the operational status of the PCI bus clocks, bit 0 (SEC_CLK_STATUS) in the clock run status register at

offset DAh (see Section 8.4.69) is read.

Since the bridge has several unique features associated with the PCI bus interface, the system designer must

consider the following interdependencies between these features and the CLKRUN feature:

www.ti.com

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

Submit Document Feedback

119

Product Folder Links: XIO2001

XIO2001IPNP датащи(PDF) 119 Page - Texas Instruments

XIO2001IPNP датащи(HTML) 119 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL