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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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XIO2001IPNP датащи(PDF) 113 Page - Texas Instruments |
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XIO2001IPNP датащи(HTML) 113 Page - Texas Instruments |
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113 / 145 page  8.6.15 Cache Timer Upper Limit Register Discard cached data after this number of clock cycles have passed without a read hit on the completion data buffer. See Table 8-85 for a complete description of the register contents. Device control memory window register offset: 56h Register type: Read/Clear Default value: 01C0h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 Table 8-85. Cache Timer Upper Limit Register Description BIT FIELD NAME ACCESS DESCRIPTION 15:12 RSVD R Reserved. Returns 0h when read. 11:0(1) CACHE_TIMER _UPPER_LIMIT RW Discard cached data after this number of clock cycles have passed without a read hit on the completion data buffer. (1) These bits are reset by a PCI Express reset ( PERST), a GRST, or the internally-generated power-on reset. www.ti.com XIO2001 SCPS212J – MAY 2009 – REVISED JANUARY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 113 Product Folder Links: XIO2001 |
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