XIO2001IPNP datasheet(86/145 Pages) TI2

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8.4.73 Serial IRQ Mode Control Register

This register controls the behavior of the serial IRQ controller. See Table 8-56 for a complete description of the

PCI register offset:

E0h

Read-only, Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

Table 8-56. Serial IRQ Mode Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

7:4

RSVD

Reserved. Returns 0h when read.

3:2(1)

START_WIDTH

Start frame pulse width. Sets the width of the start frame for a SERIRQ stream.

00 = 4 clocks (default)

01 = 6 clocks

10 = 8 clocks

11 = Reserved

1(1)

POLLMODE

Poll mode. This bit selects between continuous and quiet mode.

0 = Continuous mode (default)

1 = Quiet mode

0(1)

DRIVEMODE

RW Drive mode. This bit selects the behavior of the serial IRQ controller during the

recovery cycle.

0 = Drive high (default)

1 = 3-state

(1)

These bits are reset by a PCI Express reset ( PERST), a GRST, or the internally-generated power-on reset.

8.4.74 Serial IRQ Edge Control Register

This register controls the edge mode or level mode for each IRQ in the serial IRQ stream. See Table 8-57 for a

complete description of the register contents.

PCI register offset:

E2h

Read/Write

Default value:

0000h

BIT NUMBER

RESET STATE

Table 8-57. Serial IRQ Edge Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15(1)

IRQ15_MODE

IRQ 15 edge mode

0 = Edge mode (default)

1 = Level mode

14(1)

IRQ14_MODE

IRQ 14 edge mode

0 = Edge mode (default)

1 = Level mode

13(1)

IRQ13_MODE

IRQ 13 edge mode

0 = Edge mode (default)

1 = Level mode

12(1)

IRQ12_MODE

IRQ 12 edge mode

0 = Edge mode (default)

1 = Level mode

11(1)

IRQ11_MODE

IRQ 11 edge mode

0 = Edge mode (default)

1 = Level mode

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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