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SC2200 датащи(PDF) 141 Page - National Semiconductor (TI) |
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SC2200 датащи(HTML) 141 Page - National Semiconductor (TI) |
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141 / 433 page ![]() Revision 3.0 141 www.national.com SuperI/O Module (Continued) Table 4-38. Bank Selection Encoding BSR Bits Bank Selected 765432 10 0 xxxx xxx 0 1 0 xxx xxx 1 1 1 xxx x 1 x 1 1 1 xxx xx 1 1 111000 00 2 111001 00 3 Table 4-39. Bank 1 Register Map Offset Type Name 00h R/W LBGD(L). Legacy Baud Generator Divisor Port (Low Byte) 01h R/W LBGD(H). Legacy Baud Generator Divisor Port (High Byte) 02h --- RSVD. Reserved 03h W LCR1. Line Control R/W BSR1. Bank Select 04h-07h --- RSVD. Reserved 1. When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 4-38 on page 141. Table 4-40. Bank 2 Register Map Offset Type Name 00h R/W BGD(L). Baud Generator Divisor Port (Low Byte) 01h R/W BGD(H). Baud Generator Divisor Port (High Byte) 02h R/W EXCR1. Extended Control1 03h R/W BSR. Bank Select 04h R/W EXCR2. Extended Control 2 05h --- RSVD. Reserved 06h RO RXFLV. RX_FIFO Level 07h RO TXFLV. TX_FIFO Level Table 4-41. Bank 3 Register Map Offset Type Name 00h RO MRID. Module and Revision ID 01h RO SH_LCR. Shadow of LCR 02h RO SH_FCR. Shadow of FIFO Control 03h R/W BSR. Bank Select 04h-07h --- RSVD. Reserved |
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