SC2200 datasheet(51/433 Pages) NSC

51 / 433 page

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Signal Definitions (Continued)

2.2

STRAP OPTIONS

Several balls are read at power-up that set up the state of

the SC2200. These balls are typically multiplexed with

other functions that are outputs after the power-up

sequence is complete. The SC2200 must read the state of

the balls at power-up and the internal PU or PD resistors

do not guarantee the correct state will be read. Therefore, it

is required that an external PU or PD resistor with a value

of 1.5 K

Ω be placed on the balls listed in Table 2-6. The

value of the resistor is important to ensure that the proper

state is read during the power-up sequence. If the ball is

not read correctly at power-up, the SC2200 may default to

a state that causes it to function improperly, possibly result-

ing in application failure.

Table 2-6. Strap Options

Strap

Option

Muxed With

Ball No.

Nominal

Internal

PU or PD

External PU/PD Strap Settings

EBGA

TEPBGA

Strap = 0 (PD)

Strap = 1 (PU)

CLKSEL0

RD#

PD100

See Table 3-7 on page 95 for

CLKSEL strap options.

GCB+I/O Offset 1Eh[9:8] (aka

CCFC register bits [9:8]) (RO):

Value programmed at reset by

CLKSEL[1:0].

GCB+I/O Offset 10h[3:0] (aka

MCCM register bits [3:0]) (RO):

Value programmed at reset by

CLKSEL[3:0].

GCB+I/O Offset 1Eh[3:0] (aka

CCFC register bits [3:0]) (R/W,

but write not recommended):

Value programmed at reset by

CLKSEL[3:0].

Note: Values for GCB+I/O Offset

10h[3:0] and 1Eh[3:0] are not the

same.

CLKSEL1

SOUT1

B27

AF3

PD100

CLKSEL2

SOUT2

AK3

D29

PD100

CLKSEL3

SYNC

AL13

P30

PD100

BOOT16

ROMCS#

PD100

Enable boot

from 8-bit ROM

Enable boot

from 16-bit

ROM

GCB+I/O Offset 34h[3] (aka MCR

strap setting.

GCB+I/O Offset 34h[14] (R/W):

Used to allow the ROMCS# width

to be changed under program

control.

TFT_PRSNT

SDATA_OUT

AK13

P29

PD100

TFT not muxed

onto Parallel

Port

TFT muxed

onto Parallel

Port

GCB+I/O Offset 30h[23] (aka

PMR register bit 23) (R/W):

Reads back strap setting.

LPC_ROM

PCICLK1

PD100

Disable boot

from ROM on

LPC bus

Enable boot

from ROM on

LPC bus

F0BAR1+I/O Offset 10h[15]

(R/W): Reads back strap setting

and allows LPC ROM to be

changed under program control.

FPCI_MON

PCICLK0

PD100

Disable Fast-

PCI, INTR_O,

and SMI_O

monitoring sig-

nals.

Enable Fast-

PCI, INTR_O,

and SMI_O

monitoring sig-

nals. (Useful

during debug.)

GCB+I/O Offset 34h[30] (aka

MCR register bit 30) (RO): Reads

back strap setting.

Note: For

normal

operation,

strap this signal low using

a1.5 K

Ω resistor.

DID0

GNT0#

PD100

Defines the system-level chip ID.

GCB+I/O Offset 34h[31,29] (aka

MCR register bits 31 and 29)

(RO): Reads back strap setting.

Note:

GNT0#must haveaPU

resistor of 1.5 K

Ω and

GNT1#must haveaPD

resistor of 1.5 K

Ω.

DID1

GNT1#

PD100

Note: Accuracy of internal PU/PD resistors: 80K to 250K.

Location of the GCB (General Configuration Block) cannot be determined by software. See the

SC2200 Thin Client On a Chip

device errata document.

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