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SC2200 датащи(PDF) 24 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
номер детали SC2200
подробное описание детали  Thin Client On a Chip
PDF  433 Pages
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производитель  NSC [National Semiconductor (TI)]
домашняя страница  http://www.national.com
Logo NSC - National Semiconductor (TI)

SC2200 датащи(HTML) 24 Page - National Semiconductor (TI)

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24
Revision 3.0
Signal Definitions (Continued)
C202
IDE_DATA9
I/O
INTS1,
TS1/4
VIO
PMR[24] = 0
DDC_SDA
I/O
INT,
OD4
PMR[24] = 1
C21
IDE_IOR0#
O
O1/4
VIO
PMR[24] = 0
TFTD10
O
O1/4
PMR[24] = 1
C22
IDE_DATA6
I/O
INTS1,
TS1/4
VIO
PMR[24] = 0
IRQ9
I
INTS1
PMR[24] = 1
C23
IDE_DATA3
I/O
INTS1,
TS1/4
VIO
PMR[24] = 0
TFTD12
O
O1/4
PMR[24] = 1
C24
IDE_DREQ0
I
INTS1
VIO
PMR[24] = 0
TFTD8
O
O1/4
PMR[24] = 1
C25
IDE_DACK0#
O
O1/4
VIO
PMR[24] = 0
TFTD0
O
O1/4
PMR[24] = 1
C26
IDE_ADDR1
O
O1/4
VIO
PMR[24] = 0
TFTD2
O
O1/4
PMR[24] = 1
C27
OVER_CUR#
I
INTS
VIO
---
C28
PLL6B
I/O
INTS,
TS2/5
VIO
PMR[29] = 0
TEST1
O
O2/5
PMR[29] = 1
C29
VIO
PWR
---
---
---
C30
X32I
I
WIRE
VBAT
---
C31
VPLL3
PWR
---
---
---
D1
PCIRST#
O
OPCI
VIO
---
D2
GNT1#
O
OPCI
VIO
---
DID1
I
(PD100)
INSTRP
Strap (See Table 2-
6onpage 51.)
D3
PCICLK0
O
OPCI
VIO
---
FPCI_MON
I
(PD100)
INSTRP
Strap (See Table 2-
6onpage 51.)
D4
GNT0#
O
OPCI
VIO
---
DID0
I
(PD100)
INSTRP
Strap (See Table 2-
6onpage 51.)
D5
AD25
I/O
INPCI,
OPCI
VIO
Cycle Multiplexed
D1
I/O
INPCI,
OPCI
D6
AD20
I/O
INPCI,
OPCI
VIO
Cycle Multiplexed
A20
O
OPCI
D7
AD18
I/O
INPCI,
OPCI
VIO
Cycle Multiplexed
A18
O
OPCI
D8
C/BE2#
I/O
(PU22.5)
INPCI,
OPCI
VIO
Cycle Multiplexed
D10
I/O
(PU22.5)
INPCI,
OPCI
Ball
No.
Signal Name
I/O
(PU/PD)
Buffer1
Type
Power
Rail
Configuration
D9
STOP#
I/O
(PU22.5)
INPCI,
OPCI
VIO
Cycle Multiplexed
D15
I/O
(PU22.5)
INPCI,
OPCI
D10
VSS
GND
---
---
---
D11
VCORE
PWR
---
---
---
D12
VSS
GND
---
---
---
D13
VCORE
PWR
---
---
---
D14
VSS
GND
---
---
---
D15
VCORE
PWR
---
---
---
D16
AD1
I/O
INPCI,
OPCI
VIO
Cycle Multiplexed
A1
O
OPCI
D17
VCORE
PWR
---
---
---
D18
VSS
GND
---
---
---
D19
VCORE
PWR
---
---
---
D20
VSS
GND
---
---
---
D21
VCORE
PWR
---
---
---
D22
VSS
GND
---
---
---
D23
IDE_DATA2
I/O
INTS1,
TS1/4
VIO
PMR[24] = 0
TFTD14
O
O1/4
PMR[24] = 1
D24
IDE_IOW0#
O
O1/4
VIO
PMR[24] = 0
TFTD9
O
O1/4
PMR[24] = 1
D25
IRQ14
I
INTS1
VIO
PMR[24] = 0
TFTD1
O
O1/4
PMR[24] = 1
D26
SIN1
I
INTS
VIO
---
D27
X27O
O
WIRE
VIO
---
D28
PLL2B
I/O
INT,
TS2/5
VIO
PMR[29] = 0
TEST0
O
O2/5
PMR[29] = 1
D29
X32O
O
WIRE
VBAT
---
D30
VBAT
PWR
---
---
---
D31
LED#
O
OD14
VSB
---
E1
FRAME#
I/O
(PU22.5)
INPCI,
OPCI
VIO
---
E2
PCICLK
I
INT
VIO
---
E3
REQ1#
I
(PU22.5)
INPCI
VIO
---
E4
PCICLK1
O
OPCI
VIO
---
LPC_ROM
I
(PD100)
INSTRP
Strap(SeeTable 2-
6onpage51.)
E28
AVSSPLL3
GND
---
---
---
E29
PWRBTN#
I
(PU100)
INBTN
VSB
---
E304, 5
ONCTL#
O
OD14
VSB
---
E31
GPWIO0
I/O
(PU100)
INTS,
TS2/14
VSB
---
Ball
No.
Signal Name
I/O
(PU/PD)
Buffer1
Type
Power
Rail
Configuration
Table 2-2.
432-EBGA Ball Assignment - Sorted by Ball Number (Continued)



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