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Architecture Overview (Continued)

1.1.2

Fast-PCI Bus

The GX1 module communicates with the Core Logic mod-

uleviaaFast-PCI bus that canworkatup to66 MHz.The

Fast-PCI bus is internal for the SC2200 and is connected to

the General Configuration Block.

This bus supports seven bus masters. The requests

(REQs) are fixed in priority. The seven bus masters in

order of priority are:

VIP

IDE Channel 0

IDE Channel 1

Audio

USB

External REQ0#

External REQ1#

1.1.3

Display

The GX1 module generates display timing, and controls

internal signals CRT_VSYNC and CRT_HSYNC of the

Video Processor module.

The GX1 module interfaces with the Video Processor via a

video data bus and a graphics data bus.

•Video data. The GX1 module uses the core clock,

divided by 2 or 4 (typically 100 - 133 MHz). It drives the

video data using this clock. Internal signals VID_VAL

and VID_RDY are used as data-flow handshake signals

between the GX1 module and the Video Processor.

•Graphics data. The GX1 module uses internal signal

DCLK, supplied by the PLL of the Video Processor, to

drive the 18-bit graphics-data bus of the Video

Processor. Each six bits of this bus define a different

color. Each of these six-bit color definitions is expanded

(by adding two zero LSB lines) to form an eight-bit bus,

at the Video Processor.

For more information about the GX1 module’s interface to

the Video Processor, see the "Display Controller" chapter

in the

GX1 Processor Series datasheet.

1.2

VIDEO PROCESSOR MODULE

The Video Processor provides high resolution and graphics

for a CRT or TFT/DSTN interface. The following para-

graphs provide a summary of how this Video Processor

interfaces with the other modules of the SC2200. For

detailed information about the Video Processor, see Sec-

tion 6.0 "Video Processor Module" on page 315.

1.2.1

GX1 Module Interface

The Video Processor is connected to the GX1 module in

the following way:

• The Video Processor DOTCLK output signal is used as

the GX1 module’s DCLK input signal.

• The GX1 module’s PCLK output signal is used as the

GFXCLK input signal of the Video Processor.

1.2.2

Video Input Port

The Video Input Port (VIP) within the Video Processor con-

tains a standard interface that is typically connected to a

media processor or TV encoder. The clock is supplied by

the externally connected device; typically at 27 MHz.

Video input can be sent to the GX1 module’s video frame

buffer (Capture Video mode) or can be used directly (Direct

Video mode).

1.2.3

Core Logic Module Interface

The Video Processor interfaces to the Core Logic module

for accessing PCI function configuration registers.

1.2.4

CRT DAC

The Video Processor drives three CRT DACs with up to

135M pixels per second.

The interface for these DACs can be monitored via exter-

nal balls of the SC2200. For more information, see Section

2.4.4 "CRT/TFT Interface Signals" on page 59.

1.3

CORE LOGIC MODULE

The Core Logic module is described in detail in Section 5.0

"Core Logic Module" on page 150.

The Core Logic module is connected to the Fast-PCI bus. It

uses signal AD28 as the IDSEL for all PCI configuration

functions except for USB which uses AD29.

1.3.1

Other Interfaces of the Core Logic Module

All the following interfaces of the Core Logic module are

implemented via external balls of the SC2200. Each inter-

face is listed below with a reference to the descriptions of

the relevant balls.

• IDE: See Section 2.4.9 "IDE Interface Signals" on page

68.

• AC97: See Section 2.4.14 "AC97 Audio Interface

Signals" on page 73.

• PCI: See Section 2.4.6 "PCI Bus Interface Signals" on

page 61.

• USB: See Section 2.4.10 "Universal Serial Bus (USB)

Interface Signals" on page 69. The USB function uses

signal AD29 as the IDSEL for PCI configuration.

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