SC2200 datasheet(66/433 Pages) NSC

66 / 433 page

www.national.com

Revision 3.0

Signal Definitions (Continued)

2.4.7

Sub-ISA Interface Signals

Signal Name

Ball No.

Type

Description

Mux

EBGA

TEPBGA

A[23:0]

See

Table 2-3

on page

32.

See

Table 2-5

on page

47.

Address Lines

AD[23:0]

D15

See

Table 2-3

on page

32.

See

Table 2-5

on page

47.

I/O

Data Bus

STOP#

D14

IRDY#

D13

TRDY#

D12

PAR

D11

C/BE3#

D10

C/BE2#

C/BE1#

C/BE0#

D[7:0]

AD[31:24]

BHE#

Byte High Enable. With A0, defines byte

accessed for 16 bit wide bus cycles.

DEVSEL#

IOCS1#

D10

I/O Chip Selects

GPIO1+TFTD12

AL12

N30

AB1D+GPIO1

IOCS0#

A10

GPIO17+TFTDCK

ROMCS#

C30

ROM or Flash ROM Chip Select

BOOT16 (Strap)

DOCCS#

DiskOnChip or NAND Flash Chip Select

GPIO20+TFTD0

AJ13

N31

AB1C+GPIO20

TRDE#

D11

Transceiver Data Enable Control. Active

low for Sub-ISA data transfers. The signal

timing is as follows:

• In areadcycle,TRDE# has thesame

timing as RD#.

• In a write cycle, TRDE# is asserted (to

active low) at the time WR# is asserted. It

continues being asserted for one PCI

clock cycle after WR# has been negated,

then it is negated.

GPIO0

RD#

Memory or I/O Read. Active on any read

cycle.

CLKSEL0 (Strap)

WR#

Memory or I/O Write. Active on any write

cycle.

---

IOR#

I/O Read. Active on any I/O read cycle.

DOCR#+GPIO14

IOW#

I/O Write. Active on any I/O write cycle.

DOCW#+GPIO15

DOCR#

DiskOnChip or NAND Flash Read. Active

on any memory read cycle to DiskOnChip.

IOR#+GPIO14

DOCW#

DiskOnChip or NAND Flash Write. Active

on any memory write cycle to DiskOnChip.

IOW#+GPIO15

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