SC2200 datasheet(91/433 Pages) NSC

91 / 433 page

Revision 3.0

www.national.com

General Configuration Block (Continued)

3.4

HIGH-RESOLUTION TIMER

The SC2200 provides an accurate time value that can be

used as a time stamp by system software. This time is

called the High-Resolution Timer. The length of the timer

value can be extended via software. It is normally enabled

while the system is in the C0 and C1 states. Optionally,

software can be programmed to enable use of the High-

Resolution Timer during C3 state and/or S1 state as well.

In all other power states the High-Resolution Timer is dis-

abled.

3.4.1

Functional Description

The High-Resolution Timer is a 32-bit free-running count-

up timer that uses the oscillator clock or the oscillator clock

divided by 27. Bit TMCLKSEL of the TMCNFG register

(Offset 0Dh[1]) can be set via software to determine which

clock shouldbeusedfor theHigh-Resolution Timer.

When the most significant bit (bit 31) of the timer changes

from 1 to 0, bit TMSTS of the TMSTS register (Offset

0Ch[0]) is set to 1. When both bit TMSTS and bit TMEN

(Offset 0Dh[0]) are 1, an interrupt is asserted. Otherwise,

the interrupt is deasserted. This interrupt enables software

emulation of a larger timer.

The High-Resolution Timer interrupt is routed to an IRQ

signal. The IRQ signal is programmable via the INTSEL

ter, see section Section 3.2 "Multiplexing, Interrupt Selec-

tion, and Base Address Registers" on page 81.

System software uses the read-only TMVALUE register

(Offset 08h[31:0]) to read the current value of the timer.

The TMVALUE register has no default value.

The input clock (derived from the 27 MHz crystal oscillator)

is enabled when:

• The GX1 module’s internal SUSPA# signal is 1.

• The GX1 module’s internal SUSPA# signal is 0 and bit

TM27MPD (Offset 0Dh[2]) is 0.

The input clock is disabled, when the GX1 module’s inter-

nal SUSPA# signal is 0 and the TM27MPD bit is 1.

For more information about signal SUSPA# see Section

3.4.2.1 "Usage Hints" on page 91 and the

GX1 Processor

Series Datasheet.

The High-Resolution Timer function resides on the internal

Fast-PCI bus and its registers are in General Configuration

Block address space. Only one complete register should

be accessed at-a-time (e.g., DWORD access should be

used for DWORD wide registers and byte access should be

used for byte-wide registers).

3.4.2

High-Resolution Timer Registers

Table 3-4 on page 92 describes the registers for the High-

Resolution Timer (TIMER).

3.4.2.1

Usage Hints

• SMM code should set bit 2 of the TMCNFG register to 1

when entering ACPI C3 state if the High-Resolution

Timer should be disabled. If this is not done, the High-

Resolution Timer is functional during C3 state.

• SMM code should set bit 2 of the TMCNFG register to 1

when entering ACPI S1 state if the High-Resolution

Timer should be disabled. If this is not done, the High-

Resolution Timer is functional during S1 state.

SC2200 датащи(PDF) 91 Page - National Semiconductor (TI)

SC2200 датащи(HTML) 91 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL