SC2200 datasheet(61/433 Pages) NSC

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Signal Definitions (Continued)

AB2D

AL11

M29

I/O

ACCESS.bus 2 Serial Data. This is the bidi-

rectional serial data signal for the interface.

Note:

If AB2D function is selected but not

used, tie AB2D high.

GPIO13

2.4.6

PCI Bus Interface Signals

Signal Name

BalL No.

Type

Description

Mux

EBGA

TEPBGA

PCICLK

PCI Clock. PCICLK provides timing for all

transactions on the PCI bus. All other PCI

signals are sampled on the rising edge of

PCICLK, and all timing parameters are

defined with respect to this edge.

---

PCICLK0

PCI Clock Outputs. PCICLK0 and PCICLK1

provide clock drives for the system at 33

MHz. These clocks are asynchronous to PCI

signals. There is low skew between all out-

puts. One of these clock signals should be

connected to the PCICLK input. All PCI clock

users in the system (including PCICLK)

should receive the clock with as low a skew

as possible.

FPCI_MON (Strap)

PCICLK1

LPC_ROM (Strap)

AD[31:24]

See

Table 2-3

on page

32.

See

Table 2-5

on page

47.

I/O

Multiplexed Address and Data. Abus

transaction consists of an address phase in

the cycle in which FRAME# is asserted fol-

lowed by one or more data phases. During

the address phase, AD[31:0] contain a physi-

cal 32-bit address. For I/O, this is a byte

address. For configuration and memory, it is

a DWORD address. During data phases,

AD[7:0] contain the least significant byte

(LSB) and AD[31:24] contain the most signifi-

cant byte (MSB).

D[7:0]

AD[23:0]

A[23:0]

C/BE3#

I/O

Multiplexed Command and Byte Enables.

During the address phase of a transaction

when FRAME# is active, C/BE[3:0]# define

the bus command. During the data phase,

C/BE[3:0]# are used as byte enables. The

byte enables are valid for the entire data

phase and determine which byte lanes carry

meaningful data. C/BE0# applies to byte 0

(LSB) and C/BE3# applies to byte 3 (MSB).

D11

C/BE2#

D10

C/BE1#

A10

C/BE0#

A13

2.4.5

ACCESS.bus Interface Signals (Continued)

Signal Name

Ball No.

Type

Description

Mux

EBGA

TEPBGA

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