SC2200 datasheet(57/433 Pages) NSC

57 / 433 page

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Signal Definitions (Continued)

DID1

Device ID. Together, the straps on these sig-

nals define the system-level chip ID.

The value of DID1 can be read in the

MCR[29]. The value of DID0 can be read in

the MCR[31].

DID0 must have a pull-up resistor of 1.5 K

Ω

and DID1 must have a pull-down resistor of

1.5 K

Ω.

GNT1#

DID0

GNT0#

POR#

J29

AH9

Power On Reset. POR# is the system reset

signal generated from the power supply to

indicate that the system should be reset.

---

X32I

C30

AJ2

I/O

Crystal Connections. Connected directly to

a 32.768 KHz crystal. This clock input is

required even if the internal RTC is not being

used. Some of the internal clocks are derived

from this clock. If an external clock is used, it

should be connected to X32I, using a voltage

level of 0 volts to VCORE +10% maximum.

X32O should remain unconnected.

---

X32O

D29

AJ3

---

X27I

A29

AG3

I/O

Crystal Connections. Connected directly to

a 27.000 MHz crystal. Some of the internal

clocks are derived from this clock. If an exter-

nal clock is used, it should be connected to

X27I, using a voltage level of 0 volts to VIO

and X27O should be remain unconnected.

---

X27O

D27

AH2

---

CLK27M

A23

AA4

27 MHz Output Clock. Output of crystal

oscillator.

IDE_DATA5

PCIRST#

PCI and System Reset. PCIRST# is the

reset signal for the PCI bus and system. It is

asserted for approximately 100 µs after

POR# is negated.

---

2.4.2

Memory Interface Signals

Signal Name

Ball No.

Type

Description

Mux

EBGA

TEPBGA

MD[63:0]

See

Table 2-3

on page

32.

See

Table 2-5

on page

47.

I/O

Memory Data Bus. The data bus lines

driven to/from system memory.

---

MA[12:0]

See

Table 2-3

on page

32.

See

Table 2-5

on page

47.

Memory Address Bus. The multiplexed

row/column address lines driven to the sys-

tem memory. Supports 256-Mbit SDRAM.

---

BA1

P31

AK14

Bank Address Bits. These bits are used to

select the component bank within the

SDRAM.

---

BA0

P30

AJ13

---

2.4.1

System Interface (Continued)

Signal Name

Ball No.

Type

Description

Mux

EBGA

TEPBGA

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