SC2200 datasheet(68/433 Pages) NSC

68 / 433 page

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Revision 3.0

Signal Definitions (Continued)

2.4.9

IDE Interface Signals

Signal Name

Ball No.

Type

Description

Mux

EBGA

TEPBGA

IDE_RST#

A22

AA1

IDE Reset. This signal resets all the devices

that are attached to the IDE interface.

TFTDCK

IDE_ADDR2

C17

IDE Address Bits. These address bits are

used to access a register or data port in a

device on the IDE bus.

TFTD4

IDE_ADDR1

C26

AE1

TFTD2

IDE_ADDR0

A26

AD3

TFTD3

IDE_DATA[15:0]

See

Table 2-3

on page

32.

See

Table 2-5

on page

47.

I/O

IDE Data Lines. IDE_DATA[15:0] transfers

data to/from the IDE devices.

TheIDE interfaceis

muxedwiththe TFT

interface. See Table

2-7onpage 52 for

details.

IDE_IOR0#

C21

IDE I/O Read Channels 0 and 1.

IDE_IOR0# is the read signal for Channel 0

and IDE_IOR1# is the read signal for Chan-

nel 1. Each signal is asserted at read

accesses to the corresponding IDE port

addresses.

TFTD10

IDE_IOR1#

AH3

D28

GPIO6+DTR2#/

BOUT2+SDTEST5#

IDE_IOW0#

D24

AD2

IDE I/O Write Channels 0 and 1.

IDE_IOW0# is the write signal for Channel 0.

IDE_IOW1# is the write signal for Channel 1.

Each signal is asserted at write accesses to

corresponding IDE port addresses.

TFTD9

IDE_IOW1#

AG4

C28

GPIO9+DCD2#+

SDTEST2

IDE_CS0#

A27

AF2

IDE Chip Selects 0 and 1. These signals are

used to select the command block registers

in an IDE device.

TFTD5

IDE_CS1#

C16

TFTDE

IDE_IORDY0

A25

AD1

I/O Ready Channels 0 and 1. When deas-

serted, these signals extend the transfer

cycle of any host register access if the

required device is not ready to respond to the

data transfer request.

Note:

selected

IDE_IORDY0

IDE_IORDY1

function(s)

but

not

used, then signal(s) should be tied

high.

TFTD11

IDE_IORDY1

AJ1

B29

GPIO10+DSR2#+

SDTEST1

IDE_DREQ0

C24

AC4

DMA Request Channels 0 and 1. The

IDE_DREQ signals are used to request a

DMA transfer from the SC2200. The direction

of transfer is determined by the

IDE_IOR/IOW signals.

Note:

selected

IDE_DREQ0/

IDE_DREQ1 function but not used,

tie IDE_DREQ0/IDE_DREQ1 low.

TFTD8

IDE_DREQ1

AJ2

C31

GPIO8+CTS2#

+SDTEST5

IDE_DACK0#

C25

AD4

DMA Acknowledge Channels 0 and 1. The

IDE_DACK# signals acknowledge the DREQ

request to initiate DMA transfers.

TFTD0

IDE_DACK1#

AH4

C30

GPIO7+RTS2#

+SDTEST0

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