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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SC2200 датащи(PDF) 46 Page - National Semiconductor (TI) |
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SC2200 датащи(HTML) 46 Page - National Semiconductor (TI) |
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46 / 433 page  www.national.com 46 Revision 3.0 Signal Definitions (Continued) AK5 GPWIO1 I/O (PU100) INTs, TS2/14 VSB --- AK66, 2 PWRCNT1 O OD14 VSB --- AK7 VSS GND --- --- --- AK8 IRRX1 I INTS VSB PMR[6] = 0 SIN3 I INTS VIO PMR[6] =1 AK96 MD1 I/O INT, TS2/5 VIO --- AK10 VSS GND --- --- --- AK116 MD7 I/O INT, TS2/5 VIO --- AK12 RASA# O O2/5 VIO --- AK13 VIO PWR --- --- --- AK14 BA1 O O2/5 VIO --- AK15 MA2 O O2/5 VIO --- AK16 VIO PWR --- --- AK176 MD35 I/O INT, TS2/5 VIO --- AK186 MD46 I/O INT, TS2/5 VIO --- AK19 VIO PWR --- --- --- AK206 MD43 I/O INT, TS2/5 VIO --- AK21 DQM5 O O2/5 VIO --- AK22 VSS GND --- --- --- AK23 MA5 O O2/5 VIO --- AK246 MD15 I/O INT, TS2/5 VIO --- AK25 VSS GND --- --- --- AK266 MD14 I/O INT, TS2/5 VIO --- AK276 MD12 I/O INT, TS2/5 VIO --- AK28 SDCLK_OUT O O2/5 VIO --- AK296 MD16 I/O INT, TS2/5 VIO --- AK30 VSS GND --- --- --- AK31 VIO PWR --- --- --- AL1 VSS GND --- --- --- AL2 VIO PWR --- --- --- AL3 VBAT PWR --- --- --- AL4 LED# O OD14 VSB --- AL5 VSB PWR --- --- --- AL6 VSBL PWR --- --- --- AL76, 2 PWRCNT2 O OD14 VSB --- AL8 SDATA_IN2 I INTS VSB F3BAR0+Memory Offset 08h[21] = 1 AL96 MD2 I/O INT, TS2/5 VIO --- AL106 MD4 I/O INT, TS2/5 VIO --- Ball No. Signal Name I/O (PU/PD) Buffer1 Type Power Rail Configuration AL11 DQM0 O O2/5 VIO --- AL12 CS0# O O2/5 VIO --- AL13 VSS GND --- --- --- AL14 MA0 O O2/5 VIO --- AL15 DQM4 O O2/5 VIO --- AL16 VSS GND --- --- --- AL176 MD38 I/O INT, TS2/5 VIO --- AL186 MD39 I/O INT, TS2/5 VIO --- AL19 VSS GND --- --- --- AL206 MD44 I/O INT, TS2/5 VIO --- AL216 MD40 I/O INT, TS2/5 VIO --- AL22 CKEA O O2/5 VIO --- AL23 MA7 O O2/5 VIO --- AL24 MA4 O O2/5 VIO --- AL256 MD8 I/O INT, TS2/5 VIO --- AL266 MD10 I/O INT, TS2/5 VIO --- AL276 MD9 I/O INT, TS2/5 VIO --- AL28 MA12 O O2/5 VIO --- AL296 MD23 I/O INT, TS2/5 VIO --- AL30 VIO PWR --- --- --- AL31 VSS GND --- --- --- 1. For Buffer Type definitions, refer to Table 8-9 "Buffer Types" on page 364. 2. Is 5V tolerant (ACK#, AFD#/DSTRB#, BUSY/WAIT#, ERR#, INIT#, PD[7:0], PE, SLCT, SLIN#/ASTRB#, STB#/WRITE#, ONCTL#, PWRCNT[2:1]). 3. The TFT_PRSNT strap determines the power-on reset (POR) state of PMR[23]. 4. The LPC_ROM strap determines the power-on reset (POR) state of PMR[14] and PMR[22]. 5. May need 5V tolerant protection at system level (DDC_SCL, DDC_SDA). 6. Is back-drive protected (MD[63:0], DPOS_PORT1, DNEG_PORT1, DPOS_PORT2, DNEG_PORT2, DPOS_PORT3, DNEG_PORT3, ACK#, AFD#/DSTRB#, BUSY/WAIT#, ERR#, INIT#, PD[7:0], PE, SLCT, SLIN#/ASTRB#, STB#/WRITE#, ONCTL#, PWRCNT[2:1]). Ball No. Signal Name I/O (PU/PD) Buffer1 Type Power Rail Configuration Table 2-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued) |
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