SC2200 datasheet(82/433 Pages) NSC

82 / 433 page

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Revision 3.0

General Configuration Block (Continued)

AC97CKEN (Enable AC97_CLK Output). This bit enables the output drive of AC97_CLK (EBGA ball AJ14 / TEPBGA ball

P31).

0: AC97_CLK output is HiZ.

1: AC97_CLK output is enabled.

TFTIDE (TFT/IDE). Determines whether certain balls are used for TFT signals or for IDE signals. Note that there are no

additional dependencies.

Ball #

0: IDE Signals

1: CRT, GPIO and TFT Signals

EBGA / TEPBGA

Name

A26 / AD3

IDE_ADDR0

TFTD3

C26 / AE1

IDE_ADDR1

TFTD2

C17 / U2

IDE_ADDR2

TFTD4

B24 / AC3

IDE_DATA0

TFTD6

A24 / AC1

IDE_DATA1

TFTD16

D23 / AC2

IDE_DATA2

TFTD14

C23 / AB4

IDE_DATA3

TFTD12

B23 / AB1

IDE_DATA4

FP_VDD_ON

A23 / AA4

IDE_DATA5

CLK27M

C22 / AA3

IDE_DATA6

IRQ9

B22 / AA2

IDE_DATA7

INTD#

A21 / Y3

IDE_DATA8

GPIO40

C20 / Y2

IDE_DATA9

DDC_SDA

A20 / Y1

IDE_DATA10

DDC_SCL

C19 / W4

IDE_DATA11

GPIO41

B19 / W3

IDE_DATA12

TFTD13

A19 / V3

IDE_DATA13

TFTD15

C18 / V2

IDE_DATA14

TFTD17

B18 / V1

IDE_DATA15

TFTD7

A27 / AF2

IDE_CS0#

TFTD5

C16 / P2

IDE_CS1#

TFTDE

C21 / Y4

IDE_IOR0#

TFTD10

D24 / AD2

IDE_IOW0#

TFTD9

C24 / AC4

IDE_DREQ0

TFTD8

C25 / AD4

IDE_DACK0#

TFTD0

A22 / AA1

IDE_RST#

TFTDCK

A25 / AD1

IDE_IORDY0

TFTD11

D25 / AF1

IRQ14

TFTD1

Table 3-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued)

Bit

Description

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