SC2200 datasheet(203/433 Pages) NSC

203 / 433 page

Revision 3.0

203

www.national.com

Core Logic Module (Continued)

Legacy Configuration SMI. If this bit is set to 1 and an access occurs to one of the configuration registers in the ISA Leg-

acy I/O register space, an SMI is generated.

0: Disable.

1: Enable.

Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].

Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[5].

Index 42h

Reserved

Reset Value: 00h

Index 43h

Delayed Transactions Register (R/W)

Reset Value: 02h

7:5

Reserved. Must be set to 0.

Enable PCI Delayed Transactions for Access to I/O Address 170h-177h (Secondary IDE Channel). PIO mode uses

repeated I/O transactions that are faster when non-delayed transactions are used.

0: I/O addresses complete as fast as possible on PCI. (Default)

1: Accesses to Secondary IDE channel I/O addresses are delayed transactions on PCI.

For best performance of VIP, this bit should be set to 1 unless PIO mode 3 or 4 are used.

Enable PCI Delayed Transactions for Access to I/O Address 1F0h-1F7h (Primary IDE Channel). PIO mode uses

repeated I/O transactions that are faster when non-delayed transactions are used.

0: I/O addresses complete as fast as possible on PCI. (Default)

1: Accesses to Primary IDE channel I/O addresses are delayed transactions on PCI.

For best performance of VIP, this bit should be set to 1 unless PIO mode 3 or 4 are used.

Enable PCI Delayed Transactions for AT Legacy PIC I/O Addresses. Some PIC status reads are long. Enabling delayed

transactions help reduce DMA latency for high bandwidth devices like VIP.

0: PIC I/O addresses complete as fast as possible on PCI. (Default)

1: Accesses to PIC I/O addresses are delayed transactions on PCI.

For best performance of VIP, this bit should be set to 1.

Enable PCI Delayed Transactions for AT Legacy PIT I/O Addresses. Some x86 programs (certain benchmarks/diagnos-

tics) assume a particular latency for PIT accesses; this bit allows that code to work.

0: PIT I/O addresses complete as fast as possible on PCI.

1: Accesses to PIT I/O addresses are delayed transactions on PCI. (Default)

For best performance (e.g., when running Microsoft Windows), this bit should be set to 0.

Reserved. Must be set to 0.

Index 44h

Reset Control Register (R/W)

Reset Value: 01h

AC97 Soft Reset. Active low reset for the AC97 codec interface.

0: AC97_RST# is driven high. (Default)

1: AC97_RST# is driven low.

6:4

Reserved. Must be set to 0.

IDE Controller Reset. Reset the IDE controller.

0: Disable.

1: Enable.

Write 0 to clear. This bit is level-sensitive and must be cleared after the reset is enabled.

IDE Reset. Reset IDE bus.

0: Disable.

1: Enable (drives outputs to zero).

Write 0 to clear. This bit is level-sensitive and must be cleared after the reset is enabled.

PCI Reset. Reset PCI bus.

0: Disable.

1: Enable.

When this bit is set to 1, the Core Logic module output signal PCIRST# is asserted and all devices on the PCI bus (including

PCIUSB) are reset. No other function within the Core Logic module is affected by this bit.

Write 0 to clear this bit. This bit is level-sensitive and must be cleared after the reset is enabled.

Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)

Bit

Description

SC2200 датащи(PDF) 203 Page - National Semiconductor (TI)

SC2200 датащи(HTML) 203 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL