SC2200 datasheet(205/433 Pages) NSC

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Core Logic Module (Continued)

PIT Counter 0.

0: Forces Counter 0 output (OUT0) to zero.

1: Allows Counter 0 output (OUT0) to pass to IRQ0.

PIT Counter 0 Enable.

0: Sets GATE0 input low.

1: Sets GATE0 input high.

2:0

ISA Clock Divisor. Determines the divisor of the PCI clock used to make the ISA clock, which is typically programmed for

approximately 8 MHz:

000: Divide by 1

100: Divide by 5

001: Divide by 2

101: Divide by 6

010: Divide by 3

110: Divide by 7

011: Divide by 4

111: Divide by 8

If PCI clock = 25 MHz, use setting of 010 (divide by 3).

If PCI clock = 30 or 33 MHz, use a setting of 011 (divide by 4).

Index 51h

ISA I/O Recovery Control Register (R/W)

Reset Value: 40h

7:4

8-Bit I/O Recovery. These bits determine the number of ISA bus clocks between back-to-back 8-bit I/O read cycles. This

count is in addition to a preset one-clock delay built into the controller.

0000: 1 PCI clock

0001: 2 PCI clocks

:::

1111: 16 PCI clocks

3:0

16-Bit I/O Recovery. These bits determine the number of ISA bus clocks between back-to-back 16-bit I/O cycles. This count

is in addition to a preset one-clock delay built into the controller.

0000: 1 PCI clock

0001: 2 PCI clocks

:::

1111: 16 PCI clocks

Index 52h

ROM/AT Logic Control Register (R/W)

Reset Value: 98h

Snoop Fast Keyboard Gate A20 and Fast Reset. Enables the snoop logic associated with keyboard commands for A20

Mask and Reset.

0: Disable snooping. The keyboard controller handles the commands.

1: Enable snooping.

6:5

Reserved. Must be set to 0.

Enable A20M# Deassertion on Warm Reset. Force A20M# high during a Warm Reset (guarantees that A20M# is deas-

serted regardless of the state of A20).

0: Disable.

1: Enable.

Enable Port 092h (Port A). Port 092h decode and the logical functions.

0: Disable.

1: Enable.

Upper ROM Size. Selects upper ROM addressing size.

0: 256K (FFFC0000h-FFFFFFFFh).

1: Use ROM Mask register (F0 Index 6Eh).

ROMCS# goes active for the above ranges whether strapped for ISA or LPC. (Refer to F0BAR1+I/O Offset 10h[15] for fur-

ther strapping/programming details.)

The selected range can then be either positively or subtractively decoded through F0 Index 5Bh[5].

Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)

Bit

Description

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